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1 features cost effective, single chip, 4-port atm ima and uni processor up to 4 ima groups over 4 t1/e1 links can be implemented supports mixed mode; links not assigned to an ima group can be used in uni mode versatile pcm interface to most popular t1 or e1 framers, reducing development time supports symmetrical and asymmetrical operation supports both common transmit clock (ctc) and independent transmit clock (itc) clocking modes supports t1 isdn lines provides utopia level 2 mphy interface (MT90221 device slaved to atm device) complies with itu g.804 recommendations for performing cell mapping into t1 and e1 transmission systems provides atm framing using cell delineation according to the itu i.432 cell delineation process provides header error control (hec) veri?ation and generation, error detection, filler cell ltering (ima mode) and idle/ unassigned cell ltering (uni mode) provides statistics to support mib connects to popular asychronous sram provides statistics on the number of hec errors 8 bit microprocessor interface, compatible with intel and motorola 3.3v operation / 5v tolerant inputs mqfp-208 pin jtag test support ordering information MT90221al 208 pin mqfp -40 c to +85 c ds5065 issue 4 december 1999 MT90221 quad ima/uni phy device figure 1 - MT90221 block diagram with built-in ima functions for 4 ima groups over up to 4 links rx external static ram utopia level 2 bus utopia i/f ctrl processor i/f 4 internal ima processors cell delineator 4 x cd circuit transmission convergence 4 x tc circuit p/s p/s t1/e1 framers 2.048 or 1.544 mb/s 4 serial pcm ports t1/e1 framers t1/e1 framers utopia fifo 4 . . . . 1 4 . . . . 1
MT90221 2 applications ? cost effective single chip solution to implement ima and uni links over t1 or e1 in all public or private uni, nni and b-ici applications ? atm edge switch ima and uni line card design ? can be used for cost reduction in current applications based on fpga implementation description the MT90221 device is targeted to systems implementing the atm forum uni speci?cations for t1/e1 rates or inverse multiplexing for atm (ima). in the MT90221 architecture, up to 4 physical and independent t1/e1 streams can be terminated through the utilization of off-the-shelf, traditional t1/ e1 framers and lius. this allows atm designers to leverage previous t1/e1 design experience, hardware and software implementation, and to select the best t1/e1 framer for the required application. the MT90221 device provides atm system designers with a ?exible architecture when implementing atm access over existing and deployed trunk interfaces, allowing a migration towards atm service technology. in addition to allowing for the design of atm uni speci?cations for t1/e1 rates, the MT90221 device is compliant with the atm forum ima speci?cations for controlling ima groups of up to 4 trunks in a single chip. the MT90221 can be con?gured to operate in different modes to facilitate the implementation of the ima function at both cpe and central of?ce sites. for systems targeting atm over t1/e1 with ima and uni operating simultaneously, the MT90221 device provides the ideal architecture and capabilities. the device provides up to 4 internal ima circuits and allows for bandwidth scaleability through the use of the utopia mphy, level 2 speci?cation at 25mhz. the implementation of the ima as per af-phy- 0086.001 inverse multiplexing for atm (ima) speci?cation version 1.1 is divided into hardware and software functions. hardware functions are implemented in the MT90221 device and software functions are implemented by the user. additional hardware functions are included to assist in the collection of statistical information to support mib implementation. hardware functions that are implemented in the MT90221 device are: ? utopia level 2 phy interface ? incoming hec veri?cation and correction (optional), ? generation of a new hec byte ? format outgoing bytes into multi-vendor pcm formats ? retrieve atm cells from the incoming multi- vendor pcm format ? perform cell delineation ? provide various counters to assist in performance monitoring hardware functions that are implemented by the ima processor in the MT90221 device are: ? transmit scheduler (one per ima group) ? generation of the tx ima data cell rate ? generation and insertion of icp cells, filler cells and stuff cells in ima mode and idle cells in uni (non-ima) mode; the icp cells are programmed by the user and the filler and idle cells are pre-de?ned ? retrieve and process icp cells in ima mode ? perform ima frame synchronization ? management of rx links to be part of the internal re-sequencer when active ? extraction of rx ima data cell rate ? veri?cation of delays between links ? perform re-sequencing of atm cells using external asynchronous static ram ? can accommodate more than 400 msec of link differential delay depending on the amount of external memory ? provide structured interrupt scheme to report various events.
MT90221 i table of contents 1.0 device architecture ......................................................................................................... .............................. 8 1.1 software functions.......................................................................................................... ........................... 8 1.1.1 link state machines....................................................................................................... .................... 8 1.1.2 ima group state machines .................................................................................................. .............. 8 1.1.3 link addition, removal or restoration..................................................................................... .......... 8 1.1.4 interrupt................................................................................................................. ............................. 8 1.1.5 signaling and rate adjustment............................................................................................. ............. 8 1.1.6 performance monitoring.................................................................................................... ................. 8 1.2 hardware functions .......................................................................................................... ......................... 9 2.0 the atm transmit path ....................................................................................................... .......................... 9 2.1 cell_in_control............................................................................................................. .............................. 9 2.2 the atm transmission convergence ............................................................................................ .......... 10 2.2.1 tx cell ram and tx fifo length ............................................................................................ ....... 10 2.3 parallel to serial pcm interface ............................................................................................ ................... 11 2.4 atm transmit path in ima mode ............................................................................................... .............. 11 2.4.1 ima frame length (m) ...................................................................................................... ............... 11 2.4.2 position of the icp cell in the ima frame................................................................................. ....... 11 2.4.3 transmit clock operation .................................................................................................. .............. 11 2.4.4 stuff cell rate ........................................................................................................... ....................... 12 2.4.5 ima data cell rate ........................................................................................................ .................. 12 2.4.6 ima controller (roundrobin scheduler)..................................................................................... ..... 12 2.4.7 icp cell generator........................................................................................................ ................... 12 2.4.8 ima frame programmable interrupt .......................................................................................... ...... 14 2.4.9 filler cell definition .................................................................................................... ...................... 14 2.4.10 tx ima group start-up.................................................................................................... ................ 14 2.4.11 tx link addition ......................................................................................................... ...................... 14 2.4.12 tx link deletion......................................................................................................... ...................... 14 2.5 atm transmit path in uni mode ............................................................................................... .............. 14 3.0 the atm receive path........................................................................................................ ......................... 15 3.1 cell delineation function ................................................................................................... ...................... 15 3.2 de-scrambling and atm cell filtering ........................................................................................ ............. 16 3.3 atm receive path in ima mode ................................................................................................ .............. 16 3.3.1 icp cell processor........................................................................................................ ................... 17 3.3.1.1 ima frame synchronization............................................................................................... ....... 17 3.3.1.2 link information........................................................................................................ ................. 18 3.3.1.3 rx oam label ............................................................................................................ .............. 18 3.3.2 out of ima frame (oif) condition .......................................................................................... ......... 18 3.3.3 link out of ima frame (lif) synchronization ............................................................................... .. 18 3.3.4 filler cell handling ...................................................................................................... ..................... 18 3.3.5 stuff cell handling ....................................................................................................... .................... 18 3.3.6 received icp cell buffer .................................................................................................. ................ 18
MT90221 ii table of contents 3.3.7 rate recovery ............................................................................................................. .................... 19 3.3.8 cell buffer/ram controller................................................................................................ ............... 19 3.3.9 cell sequence recovery .................................................................................................... ............. 19 3.3.10 delay between links ...................................................................................................... ................. 20 3.3.10.1 rx recombiner delay value .............................................................................................. ...... 20 3.3.10.2 rx maximum operational delay value..................................................................................... 20 3.3.10.3 link out of delay synchronization (lods)............................................................................... 20 3.3.10.4 negative delay values.................................................................................................. ............ 21 3.3.10.5 measured delay between links........................................................................................... ..... 21 3.3.10.6 incrementing/decrementing the recombiner delay ................................................................. 21 3.3.11 rx ima group start-up .................................................................................................... ............... 22 3.3.12 link addition ............................................................................................................ ........................ 22 3.3.13 link deletion ............................................................................................................ ........................ 22 3.3.14 disabling an ima group ................................................................................................... ................ 22 3.4 the atm receive path in uni ................................................................................................. ................ 22 4.0 description of the pcm interface............................................................................................ .................... 23 4.1 serial to parallel (s/p) and parallel to serial (p/s) converters ............................................................ .... 23 4.2 pcm system interface modes.................................................................................................. ................ 24 4.2.1 mode 2 and 6: st-bus interface for t1 ..................................................................................... ..... 25 4.2.1.1 detailed st-bus spaced mapping (3 of every 4 channels) .................................................... 25 4.2.1.2 detailed st-bus grouped mapping (24 consecutive channels)............................................. 26 4.2.1.3 detailed st-bus isdn mapping (t1 isdn modes) ................................................................. 26 4.2.2 mode 4 and 8: st-bus lnterface for e1 ..................................................................................... ..... 26 4.2.3 mode 1 and 5: generic pcm interface for t1 ................................................................................ .. 27 4.2.3.1 1.544 mhz clock......................................................................................................... .............. 27 4.2.3.2 2.048 mhz clock......................................................................................................... .............. 27 4.2.4 mode 3 and 7: generic pcm interface for e1 ................................................................................ .. 28 4.2.5 txsync signal in mode 5 and 7............................................................................................. ........ 28 4.3 clocking options ............................................................................................................ .......................... 28 4.3.1 verification of the rxsync period ......................................................................................... ......... 28 4.3.2 verification of the txsync period ......................................................................................... ......... 28 4.3.3 primary and secondary reference signals ................................................................................... .. 30 4.3.4 verification of clock activity ............................................................................................ ................. 30 4.3.5 clock selection ........................................................................................................... ..................... 30 5.0 utopia interface operation.................................................................................................. ...................... 30 5.1 atm input port .............................................................................................................. ........................... 30 5.2 atm output port ............................................................................................................. ......................... 31 5.3 utopia operation with a single phy.......................................................................................... ........... 31 5.4 utopia operation with multiple phy .......................................................................................... ............ 31 5.5 utopia operation in uni mode ................................................................................................ .............. 32 5.6 utopia operation in ima mode ................................................................................................ .............. 32 5.7 examples of utopia operation modes.......................................................................................... ......... 32
MT90221 iii table of contents 6.0 support blocks.............................................................................................................. ............................... 33 6.1 counter block............................................................................................................... ............................ 33 6.1.1 utopia input i/f counters................................................................................................. .............. 33 6.1.2 transmit pcm i/f counters ................................................................................................. ............ 33 6.1.3 receive pcm i/f counters .................................................................................................. ............ 33 6.1.4 access to the counters .................................................................................................... ................ 33 6.2 interrupt block ............................................................................................................. ............................. 34 6.2.1 irq master status and irq master enable registers..................................................................... 34 6.2.2 irq link status and irq link enable registers............................................................................. . 34 6.2.2.1 bit 7 and 6 of irq link 0 status and irq link 0 enable registers .......................................... 35 6.2.3 irq link uni overflow and irq utopia input uni overflow status registers ............................. 36 6.2.4 irq ima group overflow status and enable registers................................................................... 36 6.2.5 irq ima overflow status and rx utopia ima group fifo overflow enable registers .............. 36 6.3 register and memory map ..................................................................................................... .................. 36 6.3.1 access to the various registers ........................................................................................... ........... 36 6.3.2 direct access ............................................................................................................. ...................... 37 6.3.3 indirect access........................................................................................................... ...................... 37 6.3.4 clearing of status bits................................................................................................... ................... 37 6.3.4.1 toggle bit .............................................................................................................. .................... 37 6.3.5 test modes ................................................................................................................ ...................... 37 7.0 register descriptions ....................................................................................................... ........................... 40 7.1 utopia register description................................................................................................. ..................... 41 7.2 tx registers description.................................................................................................... ...................... 45 7.3 tx icp register description ................................................................................................. ................... 50 7.4 rx registers description .................................................................................................... ..................... 52 7.5 rx icp cell registers description ........................................................................................... ................ 56 7.6 external sram register description .......................................................................................... ............. 58 7.7 rx delay registers description .............................................................................................. ................. 60 7.8 rx recombiner registers description ......................................................................................... ............ 63 7.9 tx/rx and pll control registers description................................................................................. ........ 65 7.10 counter registers description ............................................................................................. ................... 70 7.11interrupt registers description ............................................................................................ ..................... 72 7.12 miscellaneous registers description ....................................................................................... ............... 76 8.0 application notes........................................................................................................... .............................. 77 8.1 connecting the mt90220 to various t1/e1 framers ............................................................................. .. 77 9.0 ac/dc characteristics....................................................................................................... .......................... 83
MT90221 iv table of contents packaging information.......................................................................................................... .............................. 98 list of changes................................................................................................................ .................................. 100 list of abbreviations and acronyms............................................................................................. .................. 102 atm glossary ................................................................................................................... ................................. 102
MT90221 v list of figures figure 2 - pin connections ..................................................................................................... ................................ 3 figure 3 - functional block diagram -transmitter in ima mode................................................................... ........ 10 figure 4 - functional block diagram of the transmitter in uni mode ............................................................. ...... 15 figure 5 - cell delineation state diagram ...................................................................................... ...................... 15 figure 6 - sync state block diagram ............................................................................................ ..................... 16 figure 7 - the mt90220 receiver circuit in ima mode ............................................................................ ........... 17 figure 8 - example of uni mode operation ....................................................................................... .................. 23 figure 9 - pcm mode 2 and 6: st-bus interface for t1 (spaced mapping) ....................................................... 26 figure 10 - pcm mode 2 and 6: st-bus interface for t1 (grouped mapping) ................................................... 26 figure 11 - pcm mode 4 and 8: st-bus interface for e1 .......................................................................... ......... 27 figure 12 - mode 1 and 5: generic pcm interface for t1 ......................................................................... ........... 28 figure 13 - mode 3 and 7: generic pcm interface for e1 ......................................................................... ........... 29 figure 14 - txck and txsync output pin source options .......................................................................... ..... 29 figure 15 - atm interface to mt90220 ........................................................................................... ..................... 32 figure 16 - atm interface to multiple mt90220s ................................................................................. ................ 32 figure 17 - atm mixed-mode interface to one mt90220............................................................................ ........ 33 figure 18 - irq register hierarchy ............................................................................................. ......................... 34 figure 19 - pcm mode 2 and 4: synchronous st-bus mode.......................................................................... 78 figure 20 - pcm mode 2 and 4 ctc mode .......................................................................................... ............... 79 figure 21 - pcm mode 2 and 4: itc mode ......................................................................................... .............. 80 figure 22 - pcm mode 1 and 3: generic pcm system interface..................................................................... ... 81 figure 23 - pcm mode 5 and 7: asynchronous operations .......................................................................... ...... 82 figure 24 - st-bus functional timing diagram ................................................................................... ............... 84 figure 25 - st-bus timing diagram.............................................................................................. ...................... 85 figure 26 - generic pcm interface timing diagram ............................................................................... .............. 86 figure 27 - detailed generic pcm interface timing diagram ...................................................................... ........ 87 figure 28 - setup and hold time definition ..................................................................................... .................... 89 figure 29 - tri-state timing................................................................................................... ............................... 89 figure 30 - external memory interface timing - read cycle ...................................................................... ......... 90 figure 31 - external memory interface timing - write cycle..................................................................... ........... 91 figure 32 - cpu interface timing - read access ................................................................................. ............... 93 figure 33 - cpu interface motorola timing - write access....................................................................... ........... 94 figure 34 - cpu interface intel timing - write access.......................................................................... ............... 95 figure 35 - jtag port timing................................................................................................... ............................ 96 figure 36 - system clock and reset............................................................................................. ....................... 97 figure 37 - metric quad flat package - 208 pin ................................................................................. ................. 98
MT90221 vi list of tables pin description ................................................................................................................ ....................................... 4 pinout summary ................................................................................................................. .................................... 7 table 1 - idcr integration register value ...................................................................................... ..................... 12 table 2 - icp cell description ................................................................................................. ............................. 13 table 3 - cell acquisition time................................................................................................ ............................. 16 table 4 - differential delay for various memory configuration .................................................................. .......... 19 table 5 - conversion factors time/cell (msec) .................................................................................. ................. 20 table 6 - pcm modes............................................................................................................ ............................... 24 table 7 - pcm clock and mapping options ........................................................................................ ................. 24 table 8 - t1channel mapping using 3 channels every 4 channels .................................................................. . 25 table 9 - t1 channel mapping using 24 consecutive channels..................................................................... .... 25 table 10 - channel mapping from st-bus to e1 ................................................................................... ............. 27 table 11 - register summary.................................................................................................... ........................... 38 table 12 - utopia input link address registers ................................................................................. ............... 41 table 13 - utopia input group address registers................................................................................ ............. 41 table 14 - utopia input link phy enable register ............................................................................... ............ 41 table 15 - utopia input group phy enable register .............................................................................. .......... 42 table 16 - utopia input control register ....................................................................................... ....................... 42 table 17 - utopia output link address registers ................................................................................ ............. 42 table 18 - utopia output group address registers.............................................................................. ........... 43 table 19 - utopia output link phy enable register.............................................................................. ........... 43 table 20 - utopia output group phy enable register ............................................................................. ........ 43 table 21 - rx utopia ima group fifo overflow enable register................................................................... . 44 table 22 - rx utopia link fifo overflow enable register ........................................................................ ...... 44 table 23 - tx cell ram control register....................................................................................... ..................... 45 table 24 - tx utopia fifo level register ....................................................................................... ................. 45 table 25 - tx fifo length definition register 1 ................................................................................ ................. 45 table 26 - tx fifo length definition register 2 ............................................................................... ................. 45 table 27 - tx fifo length definition register 3 ................................................................................ ................. 46 table 28 - tx fifo length definition register 4 ............................................................................... ................. 46 table 29 - tx fifo length definition register 5 ............................................................................... ................. 46 table 30 - tx fifo length definition register 6 ................................................................................ ................. 46 table 31 - tx group control mode registers .................................................................................... ................. 47 table 32 - tx link id registers ............................................................................................... ........................... 47 table 33 - tx icp cell offset registers....................................................................................... ....................... 47 table 34 - tx idcr integration registers....................................................................................... ..................... 48 table 35 - tx link control registers ........................................................................................... ........................ 48 table 36 - tx ima control registers........................................................................................... ........................ 49 table 37 - tx ima mode status register........................................................................................ .................... 49 table 38 - tx icp cell handler register........................................................................................ ...................... 50 table 39 - tx icp cell interrupt enable register.............................................................................. .................. 50 table 40 - tx icp cell registers .............................................................................................. .......................... 51 table 41 - rx link control registers .......................................................................................... ........................ 52 table 42 - cell delineation register.......................................................................................... .......................... 52 table 43 - loss of delineation register ........................................................................................ ....................... 52 table 44 - ima frame delineation register ..................................................................................... ................... 53 table 45 - rx oam label register .............................................................................................. ....................... 53
MT90221 vii list of tables table 46 - rx oif status register............................................................................................. ......................... 53 table 47 - rx oif counter clear command register .............................................................................. .......... 54 table 48 - rx load values/link select register ................................................................................ ................ 54 table 49 - rx link ima id registers........................................................................................... ........................ 54 table 50 - rx icp cell offset register ........................................................................................ ....................... 55 table 51 - rx link frame sequence number register ............................................................................. ......... 55 table 52 - rx link scci sequence number register.............................................................................. .......... 55 table 53 - rx link oif counter value register ................................................................................. ................ 55 table 54 - rx link id number register ......................................................................................... ...................... 56 table 55 - rx state register.................................................................................................. ............................. 56 table 56 - rx icp cell type ram register 1..................................................................................... ................. 57 table 57 - icp cell type ram register 2....................................................................................... .................... 58 table 58 - rx icp cell buffer increment read pointer register ................................................................. ....... 58 table 59 - rx icp cell level fifo status register.............................................................................. ............... 58 table 60 - test mode enable register........................................................................................... ...................... 59 table 61 - sram control register .............................................................................................. ........................ 59 table 62 - rx external sram read/write data ................................................................................... .............. 59 table 63 - rx external sram read/write address 0............................................................................... ........... 60 table 64 - rx external sram read/write address 1.............................................................................. ........... 60 table 65 - rx external sram read/write address 2.............................................................................. ........... 61 table 66 - rx external sram control register.................................................................................. ................ 61 table 67 - increment/decrement delay control register......................................................................... ........... 62 table 68 - rx delay select register........................................................................................... ........................ 62 table 69 - rx delay msb register .............................................................................................. ....................... 62 table 70 - rx delay lsb register .............................................................................................. ........................ 63 table 71 - rx delay link number register ...................................................................................... .................. 63 table 72 - rx guardband/delta delay lsb register............................................................................... ............ 63 table 73 - rx guardband/delta delay msb register............................................................................... ........... 63 table 74 - rx maximum operational delay lsb register........................................................................... ........ 63 table 75 - rx maximum operational delay msb register........................................................................... ....... 64 table 76 - rx recombiner registers............................................................................................ ...................... 64 table 77 - rx recombiner delay control registers .............................................................................. ............. 64 table 78 - enable recombination status ........................................................................................ .................... 65 table 79 - rx reference link control registers ................................................................................ ................ 65 table 80 - rx idcr integration registers ...................................................................................... .................... 65 table 81 - tx pcm link control register number 2 ............................................................................... ............ 66 table 82 - tx pcm link control register number 1 ............................................................................... ............ 66 table 83 - rx pcm link control register....................................................................................... .................... 68 table 84 - pll reference control register ..................................................................................... ................... 68 table 85 - clock activity register............................................................................................ ............................ 69 table 86 - rx sync. status register........................................................................................... ........................ 69 table 87 - tx sync. status register ........................................................................................... ........................ 69 table 88 - tx clock disabled status........................................................................................... ........................ 69 table 89 - pll ref clock disabled status/device rev ........................................................................... .......... 70 table 90 - counter byte number 3 register ..................................................................................... .................. 70 table 91 - counter byte number 2 register ..................................................................................... .................. 70 table 92 - counter byte number 1 register ..................................................................................... .................. 71
MT90221 viii list of tables table 93 - select counter register ............................................................................................ ......................... 71 table 94 - counter transfer command register ................................................................................... .............. 72 table 95 - irq master status register .......................................................................................... ...................... 72 table 96 - irq master enable register ......................................................................................... ..................... 73 table 97 - irq link status registers .......................................................................................... ........................ 73 table 98 - irq link enable registers .......................................................................................... ....................... 73 table 99 - irq ima group overflow status register............................................................................. ............. 74 table 100 - irq ima group overflow enable register............................................................................ ........... 74 table 101 - irq ima overflow status registers ................................................................................. ................ 74 table 102 - irq utopia uni overflow status registers.......................................................................... ......... 75 table 103 - irq link uni overflow status registers............................................................................ .............. 76 table 104 - general status register ........................................................................................... ........................ 76 table 105 - test 1 register ................................................................................................... .............................. 76 absolute maximum conditions .................................................................................................... ......................... 83 recommended operating conditions ............................................................................................... .................... 83 dc electrical characteristics .................................................................................................. ............................... 83 ac electrical characteristics - pcm port st-bus interface mode................................................................. .. 84 ac electrical characteristics - generic pcm interface mode ..................................................................... ......... 86 ac electrical characteristics - utopia interface transmit timing............................................................... .......... 88 ac electrical characteristics - receive timing ................................................................................. ................... 88 ac electrical characteristics - external memory interface timing - read access............................................... 9 0 ac electrical characteristics - external memory interface timing - write access............................................... 91 ac electrical characteristics - cpu interface timing - read cycle.............................................................. ....... 93 ac electrical characteristics - cpu interface motorola timing - write cycle .................................................... .. 94 ac electrical characteristics - cpu interface intel timing - write cycle ....................................................... ...... 95 ac electrical characteristics - jtag port and reset pin timing ................................................................. ..... 96 ac electrical characteristics - system clock and reset......................................................................... ............. 97 metric quad flat package dimensions ............................................................................................ ..................... 99
MT90221 3 figure 2 - pin connections pin description pin # name i/o description atm input port signals (utopia transmit interface) 22, 23, 24, 25, 26, 27, 28, 29 txdata [7:0] i utopia transmit data bus. byte-wide data driven from atm layer device to MT90221. bit 7 is the msb. all arriving data between the last byte of the previous cell and the ?rst byte of the following cell (indicated by the soc signal) is ignored. 21 txsoc i utopia transmit start of cell signal. active high signal asserted by the atm layer device when txdata[7:0] contains the ?rst valid byte of the cell. after this signal is high, the following 52 bytes should contain valid data. the MT90221 waits for another txsoc signal after reading a complete cell. 132 134 136 138 140 142 144 146 148 150 152 154 156 22 24 26 168 166 164 162 160 158 20 18 16 14 12 10 8 6 4 2 170 188 186 184 182 180 176 174 172 178 190 208 206 204 202 200 196 194 192 198 rxdata_4 rxdata_3 rxdata_2 rxdata_1 rxdata_0 vdd vss rxaddr_4 rxaddr_3 rxaddr_2 rxaddr_1 rxaddr_0 vdd rxclk vss rxenb vdd vss tx_clav up_d_4 txdata_6 txdata_5 txdata_4 txdata_3 txdata_2 vss rxdata_5 rxdata_6 rxdata_7 vdd rxclav rxsoc vdd vss sr_cs_0 sr_cs 1 sr_d_0 sr_d_1 sr_d_2 vss vdd sr_d_3 sr_d_4 sr_d_5 sr_d_6 sr_d_7 sr_we sr_a_0 sr_a_1 sr_a_2 sr_a_3 sr_a_4 vss vdd sr_a_5 sr_a_6 sr_a_7 sr_a_8 sr_a_9 vss vdd sr_a_10 sr_a_11 sr_a_12 sr_a_13 vss vdd sr_a_15 sr_a_14 sr_a_16 sr_a_17 sr_a_18 refck_0 refck_1 refck_2 refck_3 vss vss pllref_0 pllref_1 test3 test4 dsti_0 rxsynci_0 vdd rxcki_0 vss rxcki_1 dsti_1 rxsynci_1 dsti_2 rxsynci_2 vss rxcki_2 vdd rxcki_3 vss dsti_3 rxsynci_3 nc nc vss nc 208 pin mqfp 130 128 126 124 122 120 118 116 114 112 110 108 106 32 30 28 94 96 98 100 102 104 34 36 38 40 42 44 46 48 50 52 92 74 76 78 80 82 86 88 90 84 72 54 56 58 60 62 66 68 70 64 txdata_0 txenb vdd txclk vss txaddr_4 txaddr_3 txaddr_2 txaddr_1 txaddr_0 up_cs up_ oe up_rw vss vdd up_d_7 up_d_6 up_d_5 up_d_3 up_d_2 up_d_1 up_d_0 vss vss reset up_a_10 up_a_9 up_a_8 up_a_7 up_a_6 up_a_5 up_a_4 up_a_3 up_a_2 up_a_1 up_a_0 vdd up_irq tdo trst tdi tms tck vss clk vdd test1 test2 vdd vss nc nc vdd nc vss nc vdd nc nc nc nc vss nc vdd nc nc vss nc txsyncio_3 dsto_3 vss txckio_3 vdd txckio_2 vss vdd nc vdd nc nc nc nc vss nc vdd nc vss nc nc dsto_0 txsyncio_0 vdd txckio_0 vss txckio_1 vdd dsto_1 txsyncio_1 dsto_2 txsyncio_2 vss vss txdata_7 txdata_1 txsoc
MT90221 4 32 txclk i utopia transmit clock. transfer clock from the atm layer device to the MT90221 which synchronizes data transfers on txdata[1:0]. this signal is the clock of the incoming data. data is sampled on the rising edge of this signal. 30 txenb i utopia transmit data enable. active low signal asserted by the atm layer device during cycles when txdata contains valid cell data. 20 txclav o utopia transmit cell available indication signal. for cell-level ?ow control in a mphy environment, txclav is an active high tri-stateable signal from the MT90221 to the atm layer device. a polled MT90221 drives txclav only during each cycle following one with its address on the txaddr lines. the polled MT90221 asserts txclav high to indicate it can accept the transfer of a complete cell, otherwise it de- asserts the signal. 34, 35, 36, 37, 38 txaddr [4:0] i transmit address .five bit wide true data driven from the atm to the phy layer to poll and select the appropriate MT90221. txaddr[4] is the msb. each MT90221 keeps its addresses. the value for the tx and rx portions of the MT90221 can be different atm output port signals (utopia receive interface) (see note 1) 205, 206, 207, 2, 3, 4, 5, 6 rxdata [7:0] o utopia receive data bus. byte-wide data driven from MT90221 to atm layer device. rxdata[1] is the msb. to support multiple phy con?gurations, rxdata is tri-stateable, enabled only in cycles following those with rxenb asserted. 202 rxsoc o utopia receive start of cell signal. active high asserted by the MT90221 when rxdata contains the ?rst valid byte of a cell. to support multiple phy con?gurations, rxsoc is tri-stateable, enabled only in cycles following those with rxenb asserted. 15 rxclk i utopia receive byte clock . this signal is the clock of the outgoing data. data changes after the rising edge of this signal. the rxclk needs to be synchronized with the system clock. 17 rxenb i utopia receive data enable. active low signal asserted by the atm layer device to indicate that rxdata[3:0] and rxsoc will be sampled at the end of the next cycle. in multiple phy con?gurations, rxenb* is used to tri-state rxdata and rxsoc MT90221 outputs. in that case, rxdata and rxsoc would be enabled only in cycles following those with rxenb asserted. 203 rxclav o utopia receive cell available indication signal. for cell-level ?ow control in a mphy environment, rxclav is an active high tri-stateable signal from the MT90221 to atm layer device. a polled MT90221 drives rxclav only during each cycle following one with its address on the txaddr lines. the polled MT90221 asserts rxclav high to indicate it has a complete cell available for transfer to the atm layer device, otherwise it de-asserts the signal. this signal indicates cycles when there is valid information on rxdata / rxsoc. 9, 10, 11, 12, 13 rxaddr [4:0] i receive address . five bit wide true data driven from the atm to phy layer to select the appropriate MT90221. rxaddr[4] is the msb. each MT90221 keeps its address. the value for the tx and rx portions of the MT90221 can be different. receiver static memory interface signals (see note 1) 188, 189, 190, 191, 192, 195, 196,197 sr_d [7:0] i/o static memory data bus . data bus to exchange data between the MT90221 and the external static memory. pin description (continued) pin # name i/o description
MT90221 5 162, 163, 164, 165, 166, 169, 170, 171, 172, 175, 176, 177, 178, 179, 182, 183, 184, 185, 186 sr_a [18:0] o static memory address bus . the signal is used to select an entry in the external static memory. 187 sr_w eo static memory read/not write . if low, data is written from the MT90221 to the memory. if high, data is read from the memory to the MT90221. 198, 199 sr_cs_1, 0o static memory chip control signal . processor interface signals (see note 2) 44, 45, 46, 47, 48, 49, 50, 51 up_d [7:0] i/o processor data bus . data bus to exchange data between the MT90221 and a local processor. 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65 up_a [10:0] i processor address bus . they are used to select the internal registers and memory positions of the MT90221. 41 up_r/ w or up_wr i processor read/not write. motorola mode. this is an input signal. if low, data is written from the processor to the MT90221. if high, data is read from the MT90221 to the processor. processor not write (intel mode). this is an input signal. if low, data is written from the processor to the MT90221. de-asserting this signal to high will terminate a write cycle. 40 up_ oe or up_rd i output enable motorola mode. this is an input signal. this signal should be tied to gnd for motorola timing mode. processor not read (intel mode). this is an input signal. if low, data is read from the MT90221. 39 up_cs i processor chip select . this is an active low input signal. if this signal is high, the MT90221 ignores all other signals on its processor bus. if this signal is low, the MT90221 accepts the signals on its processor bus. de-asserting this signal to high will terminate an access cycle. 67 up_irq o processor interrupt request . if this signal is low, the MT90221 signals to the processor that an interrupt condition is pending inside the MT90221. otherwise no interrupt is pending inside the MT90221. open drain signal. pcm interface signals 99,107, 109,116 dsto [3:0] o serial pcm data output 3-0 . a 1.544 mbit/s or 2.048 mbps serial stream which contain 24 (t1) or 32 (e1) pcm or data channels received on t1 or e1 line. the output is set to high impedance for unused channels and if the link is not used. 136, 143, 145, 151 dsti [3:0] i serial pcm data input 3-0 . a 1.544 mbit/s or 2.048 mbps serial stream which contains the 24 (t1) or 32 (e1) pcm or data channels on t1 or e1 line. pin description (continued) pin # name i/o description
MT90221 6 101, 103, 111, 113 txcki/o [3:0] i/o pcm interface transmit clock 3-0. this pin is an input for pcm modes 2, 4, 5 and 7. it is an output for interface modes 1, 3, 6 and 8 (see section 4.2, pcm system interface modes). it is the clock for serial pcm data transmission of the t1 and e1 framers. the txck source is software selectable and can be either one of the eight rxck or one of the four refck signals. it is used for internal transmit timing and should be connected to the transmit clock of the framer. 1. the txck is 4.096 mhz for st-bus applications. 2. for generic pcm interfaces (non st-bus or asynchronous line termination), these outputs can be programmed to provide either a 1.544 mhz (t1) or 2.048 mhz (t1 or e1) clock. 98, 106, 108, 115 txsyncio [3:0] i/o transmit line 8khz frame pulse 3-0 . this pin is an input for interface modes 2, 4, 5 and 7. it is an output for interface modes 1, 3, 6 and 8 (see pcm section 4.2, pcm system interface modes). it is the 8 khz reference used as transmit synchronization for the pcm system interface. when an output, the txsync is generated from the txck signal and is independent from other txsync signals. two output modes can be programmed: 1. for st-bus applications, it is a low going pulse (f0), that delimits the 32 channel frame of the st-bus interface at dsti and dsto lines (see figure 25 - st-bus timing diagram for this sync pulse). the frame pulse is typically received through the rxsync[0] pin. 2. for generic pcm interfaces, it can be programmed to generate either a positive or negative pulse polarity that lines up with the ?rst bit of the pcm system interface. 135, 142, 144, 150 rxsynci [3:0] i receive line 8khz frame pulse 3-0 . this signal represents the 8 khz reference received from the incoming t1 or e1 line. the MT90221 can be programmed to accept different 8 khz pulse formats at this input. 1. for st-bus applications, it is a low going pulse (f0), which delimits the 32 channel frame of st-bus interface at dsti and dsto lines. see stbus timing diagram for this sync pulse. 2. for generic pcm interfaces, it can be programmed to accept either positive or negative pulse polarities. 138, 140, 146, 148 rxcki [3:0] i pcm interface receive clock 3-0. this input line represents the clock for the receive serial pcm data of the t1 and e1 framers. the t1 or e1 frequency value to be received at this input clock is de?ned by the user through an internal register. 1. for st-bus applications, input pin rxcki receives the 4.096 mhz signal. 2. for generic pcm interfaces, these inputs can be programmed to accept either a 1.544 mhz (t1) or 2.048 mhz (t1 or e1) clock. 154, 155 pllref [1:0] o output reference to an external pll. see 4.3 description of the pcm interface for details. 158, 159, 160, 161 refck [3:0] i input reference clock inputs 3 to 0. receive the de-jittered transmit clock reference to be internally routed to the t1/e1 framer transmit clocks (output pins txck[3:0]. see description of the pcm interface on page 23. for more details. 80, 83 85, 87, 89, 92, 94 96, 117,118, 124, 125, 126, 127, 133, 134 nc no connect. suggest using external pull-up to reduce noise. pin description (continued) pin # name i/o description
MT90221 7 notes: 1. static memory stores the received cells. ram is used for reordering the cells 2. these signals are used to transfer data between the MT90221 and the local processor 81, 88, 90, 97, 120, 122, 129, 131 nc no connect. can be left unconnected. system signals 74 clk i system clock (25 mhz nominal) . in the MT90221, this clock is used for all internal operations of the device. 76 test1 i test1. this signal should be pulled up for normal operation. 54 reset i system reset. this is an active low input signal. it causes the device to enter the initial state. the clk signal must be active to reset the internal registers. 72 tck i jtag test clock. it should be pulled down if not used 71 tms i jtag test mode select . tms is sampled on the rising edge of tck. tms has an internal pull- up resistor. 70 tdi i jtag test data input . 68 tdo o jtag test data output . note: tdo is tristated by tms pin. 69 trst i tag test reset (active low). should be asserted low on power-up and during reset. must be high for jtag boundary-scan operation. note: this pin has an internal pull-down . 77 test2 i test2 . it should be pulled down for normal operation. 153 test3 i test3 . it should be pulled down for normal operation. 152 test4 i test4 . it should be pulled up for normal operation. not 5v tolerant pinout summary type input output i/o n.c. power ground tx utopia 16 1 rx utopia 7 10 microprocessor interface 14 1 8 external memory interface 22 8 tx pcm interface 4 8 rx pcm interface 12 pll interface 4 2 miscellaneous 10 1 no connect 24 power 25 ground 31 total 208 63 41 24 24 25 31 pin description (continued) pin # name i/o description
MT90221 8 1.0 device architecture the MT90221, supported by software, implements the atm forum inverse multiplexing for asynchronous transfer mode (ima) speci?cation. this approach minimizes the impact of any changes that might occur in the speci?cation. actions are implemented by the MT90221 and decisions by the software. the MT90221 supports the following two major modes of operation: ? the ima mode (as de?ned by the atm forum ima speci?cation) ? the user network interface (uni) mode up to four ima groups can be implemented. any of the four pcm interfaces can be assigned dynamically to any of these ima groups. a different utopia phy address is assigned to each of the ima groups. the uni mode is used to transfer the cells from the utopia interface to a pcm port without any overhead. up to 4 utopia phy addresses can be supported in uni mode. the MT90221 also supports a mixed mode where the pcm interfaces not assigned to an ima group can be used in uni mode. the ima implementation is divided into hardware and software functions. the MT90221 implements the hardware functions. the software functions are implemented by the user. the hardware and software functions are described below. notice that a number of MT90221 functions are included to assist in the collection of statistical information. this information supports the mib implementation. 1.1 software functions for the MT90221 to comply with the ima speci?cation, the following functions must be implemented by software: ? the transmit and receive link state machines (lsm) ? the ima group state machines (gsm) ? the ima group traf?c state machines (gtsm) ? the operations and maintenance (oam) functions 1.1.1 link state machines the software implemented transmit and receive lsms are independent (i.e., each link has its own lsm). lsms rely on various events from the MT90221 interface, such as cell errors, excessive delay between-links, etc.; or, from the t1 or e1 framer, such as loss of signal (los), loss of frame (lof), remote alarm indication (rai) etc. on-chip registers are used to generate the icp cells that communicate the lsm states to the far end (fe). 1.1.2 ima group state machines the ima gsms and group traf?c state machines (gtsm) must be implemented in software. one of each state machine should be implemented for each ima group. on-chip registers are used to generate the icp cells that communicate the various states to the fe. 1.1.3 link addition, removal or restoration the addition, removal or restoration of a link is controlled by software using the various control registers in the MT90221 and in the t1 or e1 framers. decisions are based on the MT90221 and t1 or e1 framers status registers. 1.1.4 interrupt the MT90221 provides numerous registers and counters to implement a polling and/or interrupt mechanism for tracking link and ima group status. this traf?c in and out information is used by the management information base (mib) for each ima group. 1.1.5 signaling and rate adjustment the microprocessor controls the operation of the t1 or e1 link by providing handshaking between the fe and near ends (ne) including such functions as signaling and loopback controls. rate adjustment is controlled by: ? adding or removing one or more t1 or e1 links ? providing feedback to the atm network for adjust- ing the atm traf?c. 1.1.6 performance monitoring software implements most of the performance monitoring. the MT90221 provides status information for: ? the cell delineation block and ima frame state machine ? the number of icp violations ? the total number of cells ? the number of idle or discarded cells.
MT90221 9 it also provides the content for received icp cells that contain some changes. the external t1 or e1 framers provide the low level status of the link. the software integrates and responds to the various events. 1.2 hardware functions the MT90221 circuitry implements the following functions: ? utopia l2 interface ? veri?cation of the incoming hec (optional) ? generation of a new hec byte ? transmit scheduler ? generation of the tx ima data cell rate (idcr) ? generation and insertion of icp cells, filler cells and stuff cells in ima mode ? generation of idle cells in uni mode (from on- chip copies of the cells) ? ?exible pcm formatting of the outgoing bytes ? retrieval of atm cells from the incoming pcm format ? cell delineation ? retrieval and processing of icp cells ? synchronization of the ima frame ? management of the internal re-sequencer rx links (when active) ? extraction of the rx idcr ? veri?cation of the delays between-links ? re-sequencing of atm cells using external static ram ? various performance monitoring counters ? 8-bit microprocessor interface (adaptable to intel or motorola interfaces) the MT90221 can be separated into four major independent blocks and three support blocks. the four major independent blocks are: ? the atm transmit path ? the atm receive path ? the pcm interface ? the utopia interface the three support blocks are: ? the counter block ? the interrupt block ? the microprocessor interface block 2.0 the atm transmit path the transmit path corresponds to a cell ?ow from the atm layer towards the t1/e1 interface. the atm cell path on the transmit side starts at the utopia l2 interface. once atm cells are received at the utopia port, the device transfers these cells to the transmit block. the MT90221 provides atm cell mapping and transmission convergence blocks to transport atm cell payloads over four ?exible pcm interface ports. it uses these pcm interface ports to communicate with most off-the-shelf t1 or e1 framers. each of the four t1/e1 links can be assigned to either an ima group or to an uni link. a single t1/e1 link cannot be assigned to more than one ima group. the functional block diagram at figure 3 illustrates the transmit function of the MT90221. 2.1 cell_in_control in general terms, the MT90221 transmit input port has the following properties: ? cell level handshaking complies with the atm forum utopia l2 speci?cation ? behaves like a utopia mphy device ? each port can be enabled or disabled independently ? generates and optionally veri?es the hec for incoming cells ? includes the atm forum polynomial when generating the hec (default option that can be disabled) ? either passes or removes incoming idle cells ? either passes or removes incoming unassigned cells ? provides a counter per utopia port for the total number of idle and unassigned cells (24 bits) ? provides a counter per utopia port for the total number of cells with wrong incoming hec (24 bits) ? provides a counter per utopia port for the total number of cells handled (24 bits) the input port can be enabled to remove (?lter) unassigned or idle cells. if unassigned or idle cell filtering is enabled, the device checks for and discards unassigned or idle cells. this function is programmed in the utopia input control register.
MT90221 10 section 5 describes the utopia interface in more detail. 2.2 the atm transmission convergence the transmit convergence (tc) function is common for both the ima and uni modes. it integrates the circuitry to support atm cell payload scrambling, hec generation and the generation of idle/filler/icp cells for use with the t1 and/or e1 trunks. each of the four MT90221 atm tc circuits can use the polynomial x 43 + 1 to scramble the atm cell payload ?eld. the MT90221 atm cell payload scrambling function can be disabled. the itu i.432 polynomial x 8 + x 2 + x + 1 is used to generate the hec ?eld of the atm cell. by default, the atm forum polynomial x 6 + x 4 + x 2 + 1 is added to the calculated hec octet. the addition of the atm forum polynomial can be disabled. the resulting calculation is then over-written on the hec ?eld and the atm cell is ready (i.e., complies with the ima transmit protocol) for transmission over the pcm interface. in cases where the tc block requests a cell to be transferred to any of the pcm interfaces and the tx utopia fifo has no cell ready for transmission, then the tc block will automatically send an idle cell (in uni) or a filler cell (in ima mode) to the line. the default values for the idle and the filler cells comply with the atm ima speci?cation and are pre- loaded in the MT90221 following a reset. the tx cell ram control register can be used to re- initialize the tx cell ram. 2.2.1 tx cell ram and tx fifo length the internal tx cell ram can hold up to 64 cells. the following six cells are reserved for MT90221 operation: ? one icp cell for each ima group for a total of four cells figure 3 - functional block diagram -transmitter in ima mode atm in cell_in_control cell ram fifo link 0 p/s p/s p/s link 0 serial streams link 1 transmitter utopia l2 interface filler cell idle cell icp cell group 1 icp cell group 2 icp cell group 3 icp cell group 4 next icp cell group 1 next icp cell group 2 next icp cell group 3 next icp cell group 4 icp cell modifier and cell scrambling icp cell modifier and cell scrambling icp cell modifier and cell scrambling link 3 icp cell handler from idcr generator micro i/f (see note 1) fifo link 1 (see note 1) fifo link 3 (see note 1) icp cell buffer ram tx utopia fifo group 3 tx utopia fifo group 0 round robin scheduler and fifo selection and adaptive shaper (1 of 4) idcr generator (1 of 4) transmitter reference link timing to cell_in_control note 1: this fifo is the tx utopia fifo when the link is configured in uni mode and it is the tx link fifo when it is configured in ima mode.
MT90221 11 ? one common filler cell used in ima mode ? one idle cell used in uni mode the remaining 58 cells can be assigned to any of the 12 tx fifos. the tx fifos are divided in 8 tx utopia fifos and 4 tx link fifos.the MT90221 implements one tx utopia fifo for each link when used in uni and one for each ima group for a total of 8 tx utopia fifos. each tx utopia fifo is associated with one tx utopia address. please refer to the paragraph 5.0 utopia interface operation for more details. in addition, for each link to be used in ima mode, an internal tx link fifo is utilized. these tx link fifos are holding the cell streams that are to be sent on each tx serial port. there is a total of 4 tx link fifos and their size is programmed on a per group basis using the tx ima control register. when a link is used in uni mode, its corresponding tx link fifo is disabled and the tx utopia fifo is used. tx utopia fifo length de?nition registers are used to set the tx utopia fifo size. a maximum of 15 cells can be assigned to any single fifo. the size of unused tx utopia fifos should be set to zero. the recommended size for the ima group tx utopia fifo is 1. in ima mode, the atm user cells are ?rst placed in the ima tx utopia fifo and then transferred, by the internal round robin scheduler, to the proper tx link fifo. the tx utopia fifo length for each link con?gured in ima mode should be set to zero. the tx ima control registers are used to set the size of the internal tx link fifo. an upper and lower level limit must be set for the internal tx link fifo. in uni mode, the atm user cells are queued in the tx utopia fifo until sent over the t1/e1 link. the recommended upper limit value for the internal tx link fifo is ?ve and the recommended lower limit is one when operating in itc clocking mode. when operating in ctc mode, the recommended upper limit value for the internal tx link fifo is six and the recommended lower limit is one. in the case where ctc mode is used and when the icp cells on all the links are sent with the same icp cell offset and when carrying a cbr-type traf?c, an upper value of 7 may be required. 2.3 parallel to serial pcm interface atm cell octet byte alignment conforms to itu g.804 recommendations for t1 or e1 framer parallel to serial format conversion. the tx pcm control and rx pcm control registers are used to select the t1 or e1 mode of operation. refer to section 4, description of the pcm interface, for more details. 2.4 atm transmit path in ima mode the MT90221 supports up to four independent ima groups. each of the four t1/e1 trunks can be assigned to any one of these ima groups. a t1/e1 trunk cannot be assigned to more than one ima group. refer to figure 3 for a functional block diagram of the transmitter. the ima transmitter splits the incoming stream into n sub-streams, where 1 n 4. each sub-stream is passed to a separate line interface device that transmits the cells on a physical link. the physical line rate is either 1.544 mbps (t1) or 2.048 mbps (e1). the transmitter inserts so-called icp cells in the various outgoing streams according to the ima speci?cation. the icp cells are inserted every m atm cells on each link. this is the task of the scheduler. 2.4.1 ima frame length (m) the ima frame length (value of m) can be 256, 128, 64, or 32. the value of m for each ima group is set by the tx group control mode registers. m is ?xed once an ima group is setup and should remain unchanged so long as that group is operational. 2.4.2 position of the icp cell in the ima frame the tx icp cell offset registers control the position of the icp cell in the ima frame for each link. this parameter should remain unchanged so long as that group is operational. 2.4.3 transmit clock operation the MT90221 supports both the common transmit clock (ctc) and independent transmit clock (itc) modes of operation. the desired mode is speci?ed by writing to the tx group control mode register. a reference link must be speci?ed in the tx group control mode register. the MT90221 introduces a stuff cell on the reference link every 2048 cells and determines the appropriate time to insert a stuff cell on the remaining group links. see paragraph 2.4.4, stuff cell rate, for more details.
MT90221 12 the clocking mode and reference link are ?xed once an ima group is setup and should remain unchanged so long as that group is operational. the reference link should not change unless problems are reported with the link. 2.4.4 stuff cell rate the stuff event algorithm differs between ctc and itc modes. in ctc mode, the stuff event is typically ?xed and appears in the same ima frame on all ima group links. in itc mode, the stuff event is determined using an adaptive algorithm that relates the level of the internal tx link fifo to that of the tx link fifo of the reference link. the MT90221 implements 2 different stuf?ng algorithms: a ?xed stuf?ng rate and an adaptive stuf?ng rate. the stuf?ng events do not happen more frequently than once every ?ve ima frames. tx group control mode register bit 3 selects either the adaptive or ?xed algorithm. bit 4 determines the timing mode declared in the icp cell. there are three possible combinations: ? ctc mode with internal fixed algorithm ? ctc mode with internal adaptive algorithm ? itc mode with internal adaptive algorithm in ctc mode, when using the fixed algorithm, the stuff event is periodic and will appear in the same ima frame, once every 2048 cells, on each link that is part of the ima group. in ctc mode, when using the adaptive algorithm, the stuff event will occur at an average rate of once every 2048 cells on each link and may not occur in the same ima frame on all the links. in itc mode, the stuff event is determined using the adaptive algorithm that relates the level of the internal tx link fifo with that of the tx link fifo of the reference link. the reference link has one stuff event every 2048 cells. the state of bit seven in the tx ima control register determines whether a stuff indication is generated in the ?rst or ?rst four frames preceding a stuff event. 2.4.5 ima data cell rate the MT90221 computes the internal tx ima data cell rate (idcr) for each ima group. the cell rate for the ima group reference link, speci?ed in the tx group control mode register, is integrated over a programmable period of time. the preferred integration period is programmed in the tx idcr integration register and the value is indicated in table 1 table 1 - idcr integration register value 2.4.6 ima controller (roundrobin scheduler) the ima controller produces the cell stream to be sent to the pcm blocks using the following four cell types: ? data cells received from the utopia port (user cells) ? filler cells ? ima icp cells with link status information ? stuff cells at an idcr clock tick, the roundrobin scheduler inserts either an icp cell, a user cell or a filler cell into the tx link fifo of the next link of the ima group, based on ascending link id numbers. an icp cell is inserted every m cells and a stuff event is inserted when indicated by the stuf?ng algorithm. if it is not time for an icp cell and if the traf?c is not enabled for the link (see bit 6 of the tx link control register), then a filler cell is inserted in the tx link fifo. if the traf?c is enabled and there is a user cell in the tx utopia fifo, then the user cell is transferred from the tx utopia fifo to the tx link fifo. if there is no user cell in the tx utopia fifo, then a filler cell is inserted in the tx link fifo. 2.4.7 icp cell generator once per ima frame, an icp cell is transmitted on each link of the ima group. the content of the icp cell is controlled both by MT90221 and software. the software content of the icp cell bytes is stored in buffer ram. a copy of the icp cell for each group is kept in the internal transmitter cell ram. the icp cell to be transmitted on each link is assembled on an as required basis under the control of the internal roundrobin scheduler and icp cell modi?er. hardware controls the following bytes of the icp cell: ? byte 5 - the hec is always calculated and inserted by the MT90221 ? byte 6 - the tx oam label is de?ned by the software and the value contained in this pcm mode preferred value tx idcr integration register t1 isdn (23 channels) 0x09 (2 16 clocks) t1 (24 channels) 0x0b (2 18 clocks) e1 (30 channels) 0x0c (2 19 clocks)
MT90221 13 location is transmitted in all icp cells, stuff cells and filler cells sent on all the links that are part of the corresponding tx ima group ? byte 7 - the tx link id register is used to set the link logical id and the cell type is determined by the internal controller on a per link basis ? byte 8 - the frame sequence number is controlled by an internal counter ? byte 9 - the tx icp cell offset register is used to set the value. this value is inserted on a per link basis ? byte 10 - the link stuff indication is inserted automatically and the advance indication option is programmed by the tx ima control register on a per link basis ? byte 11 - the scci is controlled by internal circuitry. the scci is incremented by one for each transfer of the tx icp cell from the buffer area to the tx cell ram. ? byte 13 - the value of m is programmed through the tx group control mode register ? byte 14 - the tx group control mode register is used to set the transmit timing information and de?ne the reference link ? bytes 52 and 53 - the calculated crc-10 error control bits are inserted automatically software controls all remaining bytes of the icp cells. it also maintains and updates all bytes that are not directly controlled by the MT90221. a dedicated address is reserved for each icp cell byte for each of the four ima groups. this permits direct access to any of the bytes stored in each of the four icp cell registers. refer to table 2, icp cell description, for details on the icp cell byte contents. to avoid updating or corruption problems, the internal copy of the icp cell cannot be directly accessed. icp cells are prepared in a buffer area (ram inside the MT90221) and transfer commands are issued to copy the content of the icp cell into the internal cell ram area and to start using this new icp cell. the MT90221 uses a ?ag (status bit) to indicate that this transfer is underway. changes should not be made to the content of the icp cell in the buffer area until the transfer to the internal memory is complete. the status bit is cleared during the transfer and returns to 1 on completion of the transfer. ima groups are controlled independently. when access to the icp cell of one group is prohibited, the other icp cell buffer areas can still be updated. the tx icp cell handler and tx icp interrupt enable registers are used to initiate a transfer and enable an optional interrupt to indicate when the process is complete. table 2 - icp cell description byte description control source 1-5 icp cell header content of header is under s/w control. the hec is calculated by h/w. 6 oam label s/w control 7 cell id, link id the link id is programmed through other registers and inserted by h/w 8 ima frame sequence hardware control 9 icp cell offset h/w control. (programmed by s/w through other registers) 10 link stuff indication h/w control 11 status change indic. h/w control 12 ima id s/w control 13 group status and control s/w control except for value of m 14 sync. info. h/w control (programmed by s/w through other registers) 15 test control s/w control 16 tx test pattern s/w control 17 rx test pattern s/w control 18-49 link status and control s/w control 50 unused s/w control 51 end-to-end channel s/w control 52-53 crc error control h/w calculation
MT90221 14 the scci ?eld is incremented by one for each transfer command performed which includes a change in at least one byte of the icp cell. 2.4.8 ima frame programmable interrupt an optional interrupt is provided at the end of an ima frame to simplify software implemented changes in the group control and status ?eld. this interrupt can be enabled on an as required and per group basis to implement a frame counter. the tx icp cell handler and tx icp interrupt enable registers are used for the transfer ready and frame interrupt. 2.4.9 filler cell definition the content of the filler cell is pre-initialized and conforms with the ima speci?cation. 2.4.10 tx ima group start-up initialize the tx ima group start-up as follows: (note: the startup procedure below is given indicating the most important steps. a more detailed and complete sequence can be found in the mt90220/221 programmers manual and example code) ? con?gure the tx pcm port(s) by writing to the tx pcm link control register 1 and 2. ? write the value of m, the timing mode and the reference link number to the tx group control register corresponding to the ima group number to be initialized. ? write the link id (lid is between 0-31) to tx link id registers for each link to be used in the ima group. lid should not be changed when a group is operational. ensure each link that is part of an ima group has a unique lid (note that the MT90221 does not verify lids). ? write the icp cell offset value to tx icp cell offset registers. this value depends on the value of m. typically, the reference link will have a delay of 0 cells in the ima frame and the icp cell in each other link will be evenly spaced in a multiple of m/n cells (where m is de?ned in the ima speci?cation and n is the number of links). the offset value for an operational group should not be changed. ? write to the tx link control registers to put the link(s) in ima mode and to enable the transfer of atm user cells when required. 2.4.11 tx link addition the MT90221 supports software controlled link addition to the existing ima group. link addition is used to increase the available bandwidth. the tx pcm link control register 1 and 2, the tx link id and tx icp cell offset registers are initialized ?rst with the proper ima group information. the link is assigned to a tx ima group by writing to the lower 2 bits of the tx link control register. the bit 3, 1 and 0 of the test 2 register have to be written with the proper value. the link is then con?gured in ima mode by writing to the bit 2 of the tx link control register. the tx ima mode status register is monitored to detect when the link is reported in ima mode. when the link is in ima mode, then the bit 3, 1 and 0 of the test 2 register are reset to 0. tx link control register bit 6 determines when atm user cells can be sent. note that the test 2 register cannot be used as a read/modify/write register. the values that are written and the values that are read are independant. note also that the bit 6 of the test 2 register shulld always be set to 1. 2.4.12 tx link deletion there are two reasons to remove a link: the required bandwidth decreases or a link becomes faulty. the MT90221 supports link deactivation under software control. a link stops transmitting user cells when bit 6 of the tx link control register is set to 0. filler and icp cells will still be sent on the link. the link is removed from an ima group by ?rst setting the bit 2 of the tx link control register to 1 while keeping the original ima group number. the ima group number can be changed only when the link is reported in uni mode as reported in the tx ima mode status register. it then can be assigned to another ima group. when removing the last link of a tx ima group, the tx utopia fifo has to be empty. this can easily be done by ?rst disabling the source of atm cells (atm utopia contoller), then disabling the tx utopia port using the utopia input link or group phy enable registers while still keeping the send user cell bit of the tx link control register set to 1. after a period of time corresponding to n idcr clock tick has elapsed, then the above procedure can be applied to assign the link in uni mode. the value of n depends on the size of the tx utopia fifo as de?ned in the tx fifo length de?nition registers. the level of the tx utopia fifo can be monitored using tx utopia fifo level register. then, the above procedure can be applied to assign the link in uni mode. 2.5 atm transmit path in uni mode a maximum of four independent t1/e1 interfaces can be selected in uni mode. figure 4 gives a functional block diagram of the transmitter in uni mode.
MT90221 15 atm cells received from the atm port are placed in a tx utopia fifo, waiting to be transmitted. if the idle/unassigned cell removal option is selected, these cells are dropped. if the tx utopia fifo is empty, an idle cell is sent to the output link. the content of the idle cell is pre-initialized with the header bytes set at 0x00, 0x00, 0x00 and 0x01. the payload bytes are set to 0x6a. tx utopia fifo length de?nition registers are used to set the tx utopia fifo size. the total number of cells in all the tx utopia fifos and tx link fifo (includes the links used in ima mode and the links used in uni mode) is limited to 58. idle cells are transmitted on the uni pcm interface until the bit corresponding to the link in the utopia input link phy enable register is set. then, the atm user cells are transferred from the input utopia port to the tx pcm port. 3.0 the atm receive path the receive path corresponds to the cell ?ow from the t1/e1 interfaces to the atm utopia interface. the MT90221 provides cell delineation and optional cell ?ltering to discard unassigned or idle cells on each link. the incoming cells are stored in the external ram required in ima mode to perform cell recovery due to delay variation between the links introduced by the network. 3.1 cell delineation function this block provides the circuitry necessary to perform functions such as cell delineation (cd), cell payload de-scrambling, hec veri?cation and ?ltering of idle (uni) cells. the cd circuit delineates atm cells received from the payload of the t1 or e1 frame through the pcm interface. when performing delineation, correct hec calculations are interpreted to indicate cell boundaries. the cd circuit performs a sequential byte by byte hunt for a correct hec sequence. while performing this hunt, the cell delineation state machine is in the hunt state. figure 5 depicts a state diagram of the cell delineation operation. figure 5 - cell delineation state diagram when a correct hec is found, the cd circuit locks on the cell boundary and enters the presync state. the presync state keeps checking the hec to ensure that the previous indication was not false. false indications are interpreted to mean the circuit is not tracking good atm cells. after entering the presync state, the ?rst false indication triggers a transition back to hunt state. if the presync state hec is correct, then a transition to the sync state occurs after d cells (delta in itu i.432) are correctly received. in the sync state, the cd circuit treats the incoming atm cell stream as stable and the MT90221 functions normally. while in the sync state, if an incorrect hec is obtained a consecutive times (alpha in itu i.432), cell delineation is considered lost and a transition is made back to the hunt state (see figure 6). as de?ned by the itu i.432 recommendations, the value of alpha and delta determine the robustness of the delineation method. the value of alpha and delta for the cell delineation state machine are de?ned in the cell delineation register. hunt correct hec (byte by byte) presync sync alpha consecutive incorrect hec (cell by cell) delta consecutive correct hec (cell by cell) incorrect hec (cell by cell) figure 4 - functional block diagram of the transmitter in uni mode (for link[n] where 1 n 4) atm in cell_in_control cell ram tx link [n] fifo p/s link [n] serial streams transmitter output controller and cell distribution
MT90221 16 only one set of values is de?ned for the four cell delineation state machines. the status of the cd state machine for each link is available in bits 0 and 1 of the rx cell delineation state register. the itu i.432 suggested values are: alpha = 7; and delta = 6. loss of cell delineation (lcd) is detected by counting the number of incorrect cells while in hunt state. the MT90221 provides an internal loss cell delineation register to set the threshold for this count. a value of 360 in the lcd register would correspond to 79 msec for e1 and 100 msec for t1 applications. the lcd state for each link is available in bit 1 of the irq linkstatus registers, and in bit 6 of the rx link id number register. the lcd status bit is reporting the current condition of the cell delineation state machine at the time it is read and cannot not be programmed to generate an interrupt when exiting the lcd condition. the software has to poll the status bit to determine when the condition is cleared. table 3 provides the time, in microseconds, for the cd circuit to receive a full atm cell from the t1 and e1 frame payloads. table 3 - cell acquisition time while the cell delineation state machine is in the sync state, the veri?cation circuit implements the state machine shown in figure 6. in normal operation, the hec veri?cation state machine remains in the correction state. incoming cells containing no hec errors are passed to the receive ima block (rx ima). incoming single-bit errors can be corrected if required by the application (i.e., single bit error correction can be enabled or disabled). after correction (when enabled), the resulting atm cell is passed to the rx ima block for ima sequencing control. if a single or multi bit error occurs, the state machine goes to the detection state. when a cell with a good hec is detected, the state machine returns to the correction state. the hec calculation normally includes the atm forum polynomial (x 6 + x 4 + x 2 + 1). the use of the polynomial can be disabled by writing to bit 1 of the rx link control register. 3.2 de-scrambling and atm cell filtering the cd circuit can de-scramble the cell payload ?eld. the de-scrambling algorithm can be enabled or disabled using bit 5 of the rx link control registers. the MT90221 can be programmed, using the rx link control registers, to discard received atm cells with hec error. hec error correction is optional and can be enabled by the cpu. when the option to correct an incoming hec value with 1 bit error is selected, the hec is corrected and the cell is not counted as a cell with a bad hec. if the option to remove the cells that are received with a bad hec is selected, then the incoming cells are replaced by a filler cell in ima mode. the cell is simply discarded when in uni mode. the counter is not incremented if the hec value is corrected, when the option is enabled. incoming idle and unassigned cells can be detected and dropped automatically. 3.3 atm receive path in ima mode the block diagram at figure 7 illustrates the MT90221 ima mode receive path. the receiver must rearrange the incoming bit streams from n-links (1 n 4) into a single utopia cell stream. format average cell acquisition time ( m s) t1 276 e1 221 figure 6 - sync state block diagram correction cell accepted detection cell discarded hcs single bit error detected (corrected or dropped) hcs multi-bit error detected (cell discarded) no hcs errors detected delta consecutive correct hcss (presync state) alpha consecutive incorrect hcss jump to hunt state atm cell delineation sync state
MT90221 17 3.3.1 icp cell processor in ima mode, the transmitter inserts special icp cells in the various outgoing streams every m atm cells to comply with the ima speci?cation. the receive block is using these icp cells to synchronize with the far end transmit side and to reconstruct the atm cell original sequence. 3.3.1.1 ima frame synchronization the mt90220 implements ima frame synchronization state machines (ifsm) for each link, as described in section 11 of the ima speci?cation. the values of alpha, beta and gamma are programmable through the frame delineation register. their values are the same for all links. after the link is programmed to be in ima mode by writing to the rx link control register, the ima frame state machine is enabled. at the same time, the parameters value of the rx link are latched in internal reference registers and are used to determine if the received icp cell meets the valid iicp cell criteria to determine ima frame synchronization. refer to section 3.3.1.2 and 3.3.1.3 for the list of links parameters. incoming icp cells are automatically detected by the icp processing block. as soon as one valid icp cell is received, the ima frame state machine moves to the ima presync state. when gamma-valid icp cells are received, the state machine moves to the ima sync state. in the ima presync state, one errored or missing icp cell causes the state machine to return to the ima hunt state. in the ima sync state, the state machine is forced to the ima hunt state by any of the following events: ? one missing icp cell ? alpha consecutive invalid icp cells ? beta consecutive errored icp cells bits 3 and 2 of the rx state register report the ima frame state machine state for a selected link. when in ima hunt mode, the information required to perform the veri?cation is extracted from the icp cells received. after the received information is validated, the ima group is con?gured by writing to the rx reference link control , the rx link control and rx recombiner registers. figure 7 - the MT90221 receiver circuit in ima mode processing icp ima cell delineation s/p frame machine rxck rxsync dsti ram controller rx scheduler utopia interface rate recovery recovered cell clk ram area icp cell with changes buffer state link info registers micro processing icp ima cell delineation s/p frame machine rxck rxsync dsti state [0] [3]
MT90221 18 3.3.1.2 link information all required veri?cation and link validation information is extracted from the icp received cells. the ima id, link id (lid), reference link number, icp cell offset and frame length can be read and validated before enabling an ima group link. software obtains this information by writing to the rx load values register to select a link and by reading the rx link ima id , rx link icp offset , rx link id and reference and rx state registers. this information can also be obtained by collecting all the received icp cells in the rx icp cell buffer and then processing the content of the icp cell (i.e., writing to the rx icp cell type ram register and then reading from the rx icp cell buffer). the contents of the link information registers should be read after enabling the rx pcm link in the rx pcm link control register and before enabling the ima mode. the link information can be accessed when a link is either in uni or ima mode. 3.3.1.3 rx oam label the rx oam label is treated differently than the other links parameters. four registers, the rx oam label registers, 1 per rx ima group, are used to de?ned the rx oam label. its value is written by the software and can be changed at any point in time. however, the rx oam label has to match the value contained in the rx icp cell for the ima frame state machine to reach the active state. 3.3.2 out of ima frame (oif) condition status bits in the rx oif status register, one bit per link, is reporting oif conditions. the status bit is latching an oif condition which corresponds to a transition of the ifsm from sync to hunt. the oif condition is reported as a status bit only and cannot generate an interrupt. the status bit is cleared by writing a 0 to the corresponding bit. there are 8 oif counters, one per link. for each oif transition, the 8-bit counter associated with the link is incremented by one. the counter can be read with indirect access when issuing a load command with the rx load values register. the counter can be cleared by writing to the rx oif counter clear command register. 3.3.3 link out of ima frame (lif) synchronization a link is declared out of ima frame (lif) synchronization state when the ifsm goes in hunt mode for gamma +2 frames after it was in sync state. this condition is latched in bit 2 of the irq link status register. refer to 6.2.2 irq link status and irq link enable registers for more details. the lif status bit is reporting the current condition of the ima frame state machine at the time it is read and cannot not be programmed to generate an interrupt when exiting the lif condition. the software has to poll the lif status bit to determine when the condition is cleared. 3.3.4 filler cell handling the MT90221 scans each incoming cell received for the filler cell indication code. filler cells are written to external ram to keep the ima frame aligned. they are automatically discarded after being read from the external ram by the recombiner. 3.3.5 stuff cell handling each incoming icp cell received is scanned for the stuff indication code. stuff cells are inserted at the transmit end as two identical and consecutive icp cells with the link stuff indication bits set as de?ned in the ima speci?cation. the MT90221 automatically discards one of the two stuff cells without storing it in external ram. the other is kept and processed as a regular icp cell. ima frame synchronization is maintained for all cases (except case 7, o-19 optional requirements) as described in figure 20 of the ima speci?cation. 3.3.6 received icp cell buffer an internal buffer is implemented to collect cells from the rx pcm links for analysis by the software. this storage unit is a circular buffer for each link and contains up to three cells per link. the buffer can selectively collect: ? all valid cells coming on a rx pcm port ? all valid icp cells ? all valid icp cells which contain new information (as indicated by the scci ?eld, valid only when the link is in ima mode). the type of cells collected is de?ned in the rx icp cell type ram registers. a status bit and a maskable irq alerts the software when a new cell is waiting for processing in a speci?c link. these are found in the irq link status and enable registers. valid icp cells when a link is in uni mode is determined by a valid hec byte. when in ima mode, a valid icp cell must meet the criteria de?ned in table 16 of the atm ima spec. software can directly access the cells in the rx buffer through a two-cell-wide access window. this access window can be advanced, one cell at a time, by issuing a command to move the internal pointer to the next cells. since the window accesses two cells, the last processed cell can be accessed at the
MT90221 19 windows base address and the new cell at the base address plus 0x40. the rx icp cell level fifo register is used to read the level of any of the 4 rx icp cell buffers. a 0 in this register signi?es that no new cell has been received. a 2 indicates the possibility that one or more cells have been missed (over?ow condition). the cell in the last entry of the circular buffer is the last cell that was meeting the selection criteria. if the cell fifo level is 2, it is constantly overwritten by any new valid incoming cell. the cell that is at the windows base address when the level is 0 is never overwritten as it is kept for reference. the rx icp cell buffer increment read pointer register is used to advance the access window by 1 cell at a time. upon the command, the buffer level is decreased by 1. when the level reaches 0, the window is not advanced anymore. during the start-up phase, the software can select to collect all valid icp cells coming in a rx pcm port and determine if the parameters are acceptable to proceed and start-up an ima group. in normal ima operating mode, the software will select to collect only valid icp with changes. the status and control change indication (scci) is monitored for all valid icp cells received. if the scci ?eld indicates a change in the icp cells, they are put aside for processing by software. to accelerate the processing of icp cells that contain changes, any byte of the last and next processed icp cell can be accessed directly. to reduce the total processing time by the software, only those bytes that need to be read are accessed. the storage unit keeps the last read icp cell and has room for up to three new icp cells. 3.3.7 rate recovery the MT90221 computes the internal rx ima data cell rate (idcr) for each ima group. the cell rate of the reference link is integrated over a programmable period of time. software must specify the reference link for the ima group in the rx reference link control register and the period of integration in the rx idcr integration register. refer to tx ima data cell rate in section 2.4.5. as an option, the reference link can be extracted automatically from the received icp cell. this option is selected by bit 4 of the rx reference link control registers. when this option is enabled, the rx reference link is always updated to re?ect the content of the last valid rxicp cell that was received. 3.3.8 cell buffer/ram controller the received cells are temporarily stored in external memory buffers until they can be correctly re-ordered for output. memory size depends on the number of links and the maximum delay allowed between the links. the memory requirements for different con?gurations is listed in table 4. the memory is organized in blocks of 64 bytes. each block can hold one cell. the following equation can be used to determine the maximum delay value or the required ram size for a determined delay: to simplify the ram interface and pin loading, the MT90221 supports the following six, sram control register selectable, external memory con?gurations: ? one 32 kbyte sram device ? two 32 kbyte sram devices ? one 128 kbyte sram device ? two 128 kbyte sram devices ? one 512 kbytes sram ? two 512 kbytes sram devices. to enable the correct memory access, the test mode enable register bit 7 has to be set to 1, the value 0x10 should be written to the rx delay link number register, the bit 3 of the rx external sram control register has to be set to 1 and the bit 6 of test 2 register has to be set to 1. 3.3.9 cell sequence recovery when an ima group is active, the ima recombiner manages the pointers to the external ram write and read location for the stored atm cells. a cell is read out from the buffer located in the external ram memory size (kbytes) delay (msec) t1 links e1 links 32kb 16 13 64kb 34 27 128kb 69 55 256kb 140 112 512kb 281 225 1024kb 560 451 note: assuming a guardband of 4 cells table 4 - differential delay for various memory con?guration maxdelay ramsize [] 64 ---------------------------- - 1 8 -- - 1 celltime [] =
MT90221 20 corresponding to the lowest link id (lid) of the ima group and placed in the rx utopia fifo. after a complete cell read, a read pointer is set to the buffer corresponding to the next lid. at the following idcr clock cycle, the next available cell is read. icp cells are skipped and filler cells are discarded. this operation is done in a roundrobin fashion based on the lid value for each ima group link. faulty conditions (i.e., buffer over?ow, excessive delay) are reported through the irq link status and irq utopia status registers. 3.3.10 delay between links the delay values between links are re?ecting the various transit delays though the network. in order to rebuild the original atm cell sequence, the link that exhibits less transport delay has to be stored until the data from the slowest link (link having the largest transport delay) has arrived. the link that exhibits the largest transport delay will be the link that requires the least cells to be stored. conversely, the line that exhibits the least transport delay is the link that requires the largest number of cells to be stored. indirect access is provided to internal registers which hold the various link delay values. the link number and delay type are ?rst selected by writing to the rx delay select register. after 2 system clock cycles, the 14-bit value in the rx delay msb and lsb and the rx delay link number registers are updated and can be read. the valid delay types are: the maximum delay over time , the current maximum delay and the current minimum delay for an ima group and the current delay values for any links. the delay values can be converted to time values by multiplying the number of cells by the conversion factor listed in the table 5. 3.3.10.1 rx recombiner delay value the icp cell from each link of the same ima group is used to determine the external sram read and write pointers. the distance between the read and write pointers is referred to as the recombiner delay. setting the recombiner delay to the maximum acceptable delay results in a ?xed recombiner delay that is not optimum. for example, setting recombiner delay to 25 msec when the worst case delay is 12 msec results in an additional, unnecessary delay of 13 msec. the minimum recombiner delay would be the current worst case differential delay. in the example above, the recombiner delay would be set to 12 msec. in this case, a link with larger transport delay than the current worst value cannot be added to an existing ima group: the cells from this slower link have not arrived when the cells sequence is rebuilt, as the read pointer was set using the previous worst case link. if this slower link is to be added, then the recombiner process has to stop for the time required to receive the cells on the slower link and then the recombiner process can resume. this causes disruption in the operation of the recombiner and will affect the cell delay variation (cdv). to provide an optimal recombiner delay, the MT90221 adds a guardband delay to the current worst case recombination delay when the ima group is ?rst started up. guardband delay is programmable and minimizes the number of disruptions that would otherwise occur in accommodating link delays exceeding the current worst case. the guardband delay is added to the minimum recombiner delay, when the recombiner process is enabled for the ?rst link of an ima group. the operational delay corresponds to the guardband delay added to the current worst case delay value. the guardband delay value is speci?ed for each ima group by writing to the guardband/delta delay register. it should be the smallest value possible consistent with minimizing the disruptions and the smallest allowed value is 4. when operational, the value of the guardband delay corresponds to the delay value of the link having the greater transport delay (the link where the data is the last to arrive to the MT90221). 3.3.10.2 rx maximum operational delay value the various delays on links of the same ima group are measured and compared to the programmed maximum allowable value stored in the rx maximum operational delay register for the ima group. this value corresponds to the worst delay value that is expected. this value cannot be larger than the number of cells that can be stored in the external memory. the smallest maximum allowable value is four cells. these values are independently established for each of the four ima groups. 3.3.10.3 link out of delay synchronization (lods) if a link to be added is slower and cannot be accommodated by the present guardband, an lods signal is generated and the link delay value is link type time per cell (msec) t1 isdn (23 ch. per frame) 0.288 t1 (24 ch. per frame) 0.276 e1 (30 ch. per frame) 0.221 table 5 - conversion factors time/cell (msec)
MT90221 21 reported negative. a delay is negative when the two most signi?cant bits are set to "1". the value reported is with respect to the read pointer and represents the minimum number of cells that has to be added to the present guardband before adding the link in the ima group. see paragraph 3.3.10.6 incrementing/decrementing the recombiner delay for more details. if a link to be added is faster and would cause its write pointer to be set beyond the rx maximum operational delay programmed value, then the link is reported to be faulty through an lods condition. the recombination process will not be affected as long as the amount of delay is not larger than the total number of cells in the external memory. lods will also be reported if, during operation, the delay of a link is changing to exhibits higher or lower delay which result in a negative delay value or beyond the rx maximum operating delay value. lods events are reported by the irq link status register and the selected current maximum delay register for an ima group. 3.3.10.4 negative delay values if the recombiner process is enabled for a link that is exhibiting a negative delay value then the recombiner process will be suspended until the write pointers are moved in such a way that the delay is reported with a positive value of 4. at this time the recombiner process will resume. no cells are lost. the same behavior applies if the delay value of a link which is part of the round robin process (recombiner bit on) goes negative: the recombiner process will be suspended until the delay value becomes positive with a value of 4. the latter condition can happen under severe error conditions if the recombiner process of the faulty link is not disabled. 3.3.10.5 measured delay between links the values and delay type for a selected link(s) or ima group can be read using the rx delay select register. ima group delay types include: the maximum delay over time ; the current maximum delay and the current minimum delay of an ima group. current link delay reports the current delay of a link. these values are all reported through a common rx delay register. the value is in number of cells. all the delay values include the guardband delay value. the rx delay link number register is reporting the link number associated with the delay value that is currently in the rx delay registers, with the exception for the maximum delay over time value, where the link number reported is not valid (reports value of 0). the maximum delay over time value can be reset at any time by writing a clear command to bit 5 in the rx delay select register. the differential delays can be easily obtained by subtracting the delay values of the links. 3.3.10.6 incrementing/decrementing the recombiner delay if a link to be added has a delay value which falls beyond the worst current delay value, then there are 2 options: either reject the link or re-adjust the pointers. to readjust the pointers, the number of cells to be added (delta) is speci?ed and corresponds to the amount of extra delay to be added to the current recombination delay. the additional delay is ?rst programmed in the guardband/delta delay register and then a command to increase the delay is issued (using the increment/decrement delay control register). the MT90221 device stops the recombiner process for the amount of time speci?ed and then resumes the recombiner process. no cells are lost but there is an effect on the cdv. the increment process is completed when the control bit in the increment/decrement delay control register is returned to a 0 value. if the link exhibiting the longest transmission delay is removed, the recombiner delay can be reduced accordingly. when such a correction occurs, the number of cells corresponding to the delay correction will be lost. to reduce the impact of this correction, its implementation can either be immediate or delayed. the increment/decrement delay control register is used for this purpose. the amount of delay to be removed (i.e., number of cells) in the recombiner process is controlled by the guardband/ delta delay register. alternatively, the links can all be placed in blocking mode for the transition period to avoid losing any cells. if a decrement delay command is issued which would result in a negative delay value on one or more links, the following action will take place: the read pointer is re-adjusted as required by the decrease delay command and since the delay is negative, the recombiner process is suspended until the delay on all the link are at least reaching a positive value of 4. then, the recombiner process will resume.
MT90221 22 3.3.11 rx ima group start-up a quick initialization sequence for the rx ima group could be as follows (default values can be used for some registers) (note: the startup procedure below is given indicating the most important steps. a more detailed and complete sequence can be found in the mt90220/221 programmers manual and example code). ? con?gure the sram parameters using the sram control, rx external sram control and test mode enable registers ? con?gure the cell delineation and ima frame state machines parameters by writing to the cell delineation, loss cell delineation and ima frame delineation registers ? write to the rx link control register to select the rx options ? con?gure the rx pcm port(s) by writing to the rx pcm link control register ? con?gure the rx utopia port by writing to the utopia output group phy enable and utopia outputgroup address registers ? validate the ima parameter values received over the pcm links and con?gure the link in ima mode using the rx recombiner and the rx link control register ? when ready, start the recombiner process by writing to the rx recombiner register 3.3.12 link addition the MT90221 supports software controlled link addition to the existing rx link group. such an addition can be used to increase available bandwidth. the added link receives filler cells until the far end (fe) tx side is active. during this time, the new links delay is measured and compared with the current operating limits. the link is either rejected or accepted. the operational delay can be corrected if required as described in 3.3.10.6 incrementing/ decrementing the recombiner delay. after synchronization is achieved, the added link can be included in the recombiner algorithm using bit 2 of the rx recombiner register. the link will be effectively included in the ima group when the corresponding bit in the enable recombination status register is set. a link may also be added to an ima group when the ?rst user cell is received. this is done by writing to the rx recombiner delay control register. 3.3.13 link deletion there are two reasons to deactivate a link: ? the bandwidth required decreases or ? an existing link becomes faulty. both link deactivation procedures speci?ed in the ima speci?cation are supported under the control of software. the command to disable the recombination process for a link is issued by writing to bit 2 of the rx recombiner register. if the delay of the link to be removed is not the worst delay, then no pointer correction is required and the recombiner bit (i.e., bit 2 of rx recombiner register) for the removed link should be set to 0. if it is the worst case delay, then the pointer values should be corrected to reduce the amount of additional delay introduced by the recombiner. the pointers need to be changed (advanced). this results in reducing the number of cells (the amount of time) required for the recombiner process. to reduce the impact of this correction, its implementation can either be immediate or delayed. a command in the increment/decrement delay control register is used for this purpose (refer to 3.3.10.6 incrementing/decrementing the recombiner delay, for more details). 3.3.14 disabling an ima group before an ima group can be disabled, the software should ensure that no user cells are left in memory. as part of the higher level handshaking, the tx fe should have sent filler cells for a while for the rx side to process all the user cells that could be in the external memory. the procedure to follow is to stop the recombination process and then, wait for the enable process to be reported inactive (in the enable recombination status register) before re-assigning the link to another ima group or to uni mode. 3.4 the atm receive path in uni up to four incoming t1/e1 lines can be connected to the MT90221 receiver and forwarded to the utopia l2 interface served by an external atm-layer device in uni mode. figure 8 illustrates four of the eight possible utopia ports that can be addressed through the utopia interface. the size of the rx utopia fifo is ?xed. the idle cells are automatically removed at the rx pcm block and all other valid received cells are transferred to the rx utopia fifo.
MT90221 23 4.0 description of the pcm interface to provide support for the ima asymmetrical mode, the transmit pcm blocks are independent from the receive pcm blocks. the tx port of a framer can be connected to any of the MT90221 tx utopia input ports and the rx port of a framer can be connected to any of the MT90221 rx utopia output ports. 4.1 serial to parallel (s/p) and parallel to serial (p/s) converters each t1/e1 link has a s/p and p/s unit assigned. the p/s unit takes a byte from the cell ram and converts it to a serial bit stream. the s/p unit takes a byte from the dsti input and converts it to parallel format for use by the cell delineation block. the system interface supports both the st-bus (2.048 mbps bus) and generic pcm interface. note that the st-bus is compatible with the so-called mvip mode that is supported by some t1 or e1 framer manufacturers. the MT90221 generates and receives the pcm channels only (24 or 23 with t1, 30 with e1). the control/status channels of the framers and the signaling channels are not supported by the MT90221. p/s and s/p units can be set-up differently on a per port and per direction basis (i.e. the transmit and receive function of the same port can use different con?gurations). the following features are supported: ? programming links as t1 or e1 ? using st-bus and generic pcm modes ? enabling/disabling the p/s and s/p units (if they are disabled the associated outputs are tri- stated) ? mapping t1 links, on a per port and per direction basis, to use either the ?rst 24 channels or 3 of every 4 channels (when st- bus or 2.048 clock modes are selected) ? programming t1 links to ignore timeslot 24 and reserve it for signaling (since only 23 timeslots are used to carry the atm cells, this option should be applied to all links of the same ima group) ? independently programming the polarity of rxck, txck, rxsync and txsync signals (generic pcm mode only) ? generating/accepting txsync and txclk signals to support most t1 and e1 framers (depending on the programmed mode) ? monitoring rxsync signal period and reporting the unexpected occurrence of a synchronization signal (see 4.3.1 veri?cation of the rxsync period, for more details) ? monitoring txsync signal period (when de?ned as input) and reporting the unexpected occurrence of a synchronization signal (see 4.3.2 veri?cation of the txsync period, for more details) figure 8 - example of uni mode operation . rxck rxsync dsti s/p rxck rxsync dsti rxck rxsync dsti rxck rxsync dsti utopia cell interface system clock s/p s/p s/p delineation idle cell removal cell delineation idle cell removal cell delineation idle cell removal cell delineation idle cell removal
MT90221 24 ? generating a txsync pulse on every pcm frame when de?ned as output ? assigning any tx or rx link to any ima group when the txck and txsync signals are outputs, the source for the txclk is software selectable from any of the four rxck inputs or any of the four external refcks. the txsync signal is generated from the txck and is independent from (not aligned with) the rxsync or other txsync signals. 4.2 pcm system interface modes there are 8 major modes of operation for the pcm interface. the only difference between modes 1 to 4 and modes 5 to 8 is in the direction of the txck and txsync signals. in the pcm modes 5 to 8, the direction is the opposite of what is de?ned in modes 1 to 4. the direction of the txck and txsync signals is de?ned by the bit 4 in the tx pcm link control register #2 and the pcm mode is de?ned in the tx pcm link control register #1 ? mode 1: generic pcm interface for t1 applications, txck and txsync outputs ? mode 2: st-bus interface for t1 applications, txck and txsync inputs ? mode 3: generic pcm interface for e1 applications, txck and txsync outputs ? mode 4: st-bus interface for e1 applications, txck and txsync inputs ? mode 5: generic pcm interface for t1 applications, txck and txsync inputs ? mode 6: st-bus interface for t1 applications, txck and txsync outputs ? mode 7: generic pcm interface for e1 applications, txck and txsync inputs ? mode 8: st-bus interface for e1 applications, txck and txsync outputs t1 with isdn services operation is available in pcm modes 1, 2, 5 and 6. channel 24 is not used to carry the atm cells and is reserved for signaling. in this case, 23 channels are used to carry the atm cells over the links and all the links in the ima group must have the same option selected. the signaling channel is always channel 24 in the t1 frame and its position will vary with the pcm frame length. in pcm mode 1 and 5, the clock can be either 1.544 or 2.048 mhz. if a 2.048 mhz clock is selected, the mapping of the 24 channels can be either grouped (the ?rst 24 consecutive timeslots starting with the frame pulse) or spaced (3 of every 4 timeslots, starting with the second timeslot of the 32 timeslot frame). pcm major modes tx pcm control registers 1 & 2 description reg 1 bit 6 reg 1 bit 5 reg 2 bit 4 e1/t1 st-bus/ generic txck/txsync (input/output) mode 1 0 0 0 t1 generic output mode 2 0 1 0 t1 st-bus input mode 3 1 0 0 e1 generic output mode 4 1 1 0 e1 st-bus input mode 5 0 0 1 t1 generic input mode 6 0 1 1 t1 st-bus output mode 7 1 0 1 e1 generic input mode 8 1 1 1 e1 st-bus output table 6 - pcm modes pcm mode st-bus generic clock frequency 4.096 mhz 1.544mhz 2.048 mhz mapping grouped a spaced b fixed c fixed grouped spaced fixed t1 isdn (23 channels) yes yes -- yes yes yes -- t1 clear channel (24 channels) yes yes -- yes yes yes -- e1 (30 channels) -- -- yes -- -- -- yes table 7 - pcm clock and mapping options a. "grouped" corresponds to the use of the ?rst 23 or 24 channels (timeslots) from the 32 timeslots available in a frame. b. "spaced" corresponds to the use of 3 channels every 4 channels (timeslots) from the 32 timeslots available in a frame. c. "fixed" corresponds to the use of channels 1-15 and 17-31 leaving channels (timeslots) 0 and 16 not used.
m t 9 0 2 2 1 2 5 i n p c m m o d e s 1 , 3 , 5 a n d 7 , p o l a r i t y o f c l o c k a n d s y n c h r o n i z a t i o n s i g n a l s ( t x c k , t x s y n c , r x c k a n d r x s y n c ) c a n b e s e t a s e i t h e r p o s i t i v e o r n e g a t i v e . i n t h e s t - b u s m o d e 2 , 4 , 6 a n d 8 , t h e c l o c k a n d f r a m e p u l s e a r e x e d a n d m u s t c o n f o r m t o t h e s t - b u s s p e c i c a t i o n . t h e r x c k a n d r x s y n c p i n s a r e a l w a y s d e n e d a s i n p u t s a n d a r e g e n e r a t e d b y e x t e r n a l c i r c u i t r y . 4 . 2 . 1 m o d e 2 a n d 6 : s t - b u s i n t e r f a c e f o r t 1 i n p c m m o d e 2 t h e t x c k a n d t x s y n c p i n s a r e d e n e d a s i n p u t s a n d i n p c m m o d e 6 , t h e t x c k a n d t x s y n c a r e d e n e d a s o u t p u t s . t h e r x c k a n d r x s y n c a r e a l w a y s d e n e d a s i n p u t p i n s . i n t 1 a p p l i c a t i o n s , a d s - 1 f r a m e i s 1 9 3 b i t s l o n g a n d c o r r e s p o n d s t o 1 f r a m i n g b i t a n d 1 9 2 p a y l o a d b i t s . t h e 1 9 2 p a y l o a d b i t s a r e d i v i d e d a s 2 4 c h a n n e l s o r t i m e s l o t s o f 8 b i t s e a c h . 3 1 . t w o d i f f e r e n t m a p p i n g s c h e m e s a r e s e l e c t a b l e . t h e s p a c e d m a p p i n g s c h e m e u s e s 3 o f e v e r y 4 c h a n n e l s . t h e g r o u p e d s c h e m e u s e s t h e r s t 2 4 c h a n n e l s . r e f e r t o t a b l e 8 f o r d e t a i l s o f s p a c e d d s - 1 m a p p i n g , t a b l e 9 f o r g r o u p e d d s 1 m a p p i n g . a l l u n u s e d c h a n n e l s a r e t r i - s t a t e . f r a m e p u l s e i s 8 k h z a n d s h o u l d b e a s d e n e d i n m s a n - 1 2 6 ) . i n t h e p c m m o d e 6 , t h e t x c k a n d t x s y n c p i n s a r e d e f i n e d a s o u t p u t s . t h e s o u r c e f o r t h e t x c k i s s e l e c t e d u s i n g t x p c m l i n k c o n t r o l r e g i s t e r n u m b e r 2 a n d c a n b e a n y o f t h e f o u r r x c k o r f o u r e x t e r n a l r e f c k c l o c k s . a s t h e r e i s n o p l l i n s i d e t h e m t 9 0 2 2 1 , t h e s o u r c e f r e q u e n c y h a s t o b e a v a l i d s t - b u s c l o c k s i g n a l ( i . e . , 4 . 0 9 6 m h z ) . t h e t x s y n c s i g n a l i s g e n e r a t e d b y t h e m t 9 0 2 2 1 a n d m e e t s t h e s t - b u s f o r m a t . i t i s n o t s y n c h r o n i z e d w i t h a n y o t h e r r x s y n c o r t x s y n c s i g n a l . 4 . 2 . 1 . 1 d e t a i l e d s t - b u s s p a c e d m a p p i n g ( 3 o f e v e r y 4 c h a n n e l s ) d s 1 ( t 1 ) l i n k s c o n t a i n 2 4 b y t e s o f s e r i a l v o i c e / d a t a c h a n n e l s d i s t r i b u t e d o v e r t h e 3 2 s t - b u s c h a n n e l s . o n e m a p p i n g o p t i o n u s e s 3 o f e v e r y 4 c h a n n e l s . t h e c h a n n e l s 0 , 4 , 8 , 1 2 , 1 6 , 2 0 , 2 4 a n d 2 8 o f t h e s t - b u s a r e n o t u s e d . t h e m t 9 0 2 2 1 t r i - s t a t e s t h e d s t o l i n e s d u r i n g t h e u n u s e d t i m e - s l o t s . s e e f i g u r e 9 . d s 1 t i m e s l o t s - 1 2 3 - 4 5 6 - 7 8 9 - 1 0 1 1 1 2 v o i c e / d a t a c h a n n e l s ( d s t i / o ) s t - b u s 0 x 1 2 3 4 x 5 6 7 8 x 9 1 0 1 1 1 2 x 1 3 1 4 1 5 d s 1 t i m e s l o t s - 1 3 1 4 1 5 - 1 6 1 7 1 8 - 1 9 2 0 2 1 - 2 2 2 3 2 4 v o i c e / d a t a c h a n n e l s ( d s t i / o ) s t - b u s 1 6 x 1 7 1 8 1 9 2 0 x 2 1 2 2 2 3 2 4 x 2 5 2 6 2 7 2 8 x 2 9 3 0 3 1 t a b l e 8 - t 1 c h a n n e l m a p p i n g u s i n g 3 c h a n n e l s e v e r y 4 c h a n n e l s d s 1 t i m e s l o t s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 v o i c e / d a t a c h a n n e l s ( d s t i / o ) s t - b u s 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 d s 1 t i m e s l o t s 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 - - - - - - - - v o i c e / d a t a c h a n n e l s ( d s t i / o ) s t - b u s 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 x 2 5 x 2 6 x 2 7 x 2 8 x 2 9 x 3 0 x 3 1 x t a b l e 9 - t 1 c h a n n e l m a p p i n g u s i n g 2 4 c o n s e c u t i v e c h a n n e l s t h e z a r l i n k s t - b u s h a s 3 2 c h a n n e l s n u m b e r e d 0 t o t h e z a r l i n k s t - b u s c l o c k v a l u e i s 4 . 0 9 6 m h z . t h e f i g u r e 9 o r f i g u r e 1 0 ( s e e z a r l i n k a p p l i c a t i o n n o t e
m t 9 0 2 2 1 2 6 f i g u r e 9 - p c m m o d e 2 a n d 6 : s t - b u s i n t e r f a c e f o r t 1 ( s p a c e d m a p p i n g f i g u r e 1 0 - p c m m o d e 2 a n d 6 : s t - b u s i n t e r f a c e f o r t 1 ( g r o u p e d m a p p i n g ) s t - b u s b i t c e l l s ( d s t x 0 - 3 ) s e r i a l b i t s t r e a m b i t c e l l t x s y n c 0 - 3 r x s y n c 0 - 3 t x c k 0 - 3 r x c k 0 - 3 b i t c e l l . . . . . . . . . . . . . . . . . . . . . . . . s t - b u s b i t c e l l s a t d s t x 0 - 3 c h a n . n b i t 7 s e r i a l b i t s t r e a m b i t c e l l t x s y n c 0 - 3 r x s y n c 0 - 3 t x c k 0 - 3 r x c k 0 - 3 b i t c e l l . . . . . . . . . . . . . . . . . . . . . . . . c h a n . n - 1 b i t 0 c h a n . n + 1 b i t 7 c h a n . n b i t 0 c h a n . 0 b i t 7 c h a n . 3 1 b i t 0 c h a n . 1 b i t 7 c h a n . 0 b i t 0 n o t e : t h e v a l u e n i s 0 , 4 , 8 , 1 2 , 1 6 , 2 0 , 2 4 o r 2 8 a n d c o r r e s p o n d s t o t h e u n u s e d c h a n n e l s . u n u s e d o r h i g h i m p e d a n c e u n u s e d o r h i g h i m p e d a n c e u n u s e d o r h i g h i m p e d a n c e u n u s e d o r h i g h i m p e d a n c e s e r i a l b i t s t r e a m b i t c e l l b i t c e l l b i t c e l l u n u s e d o r h i g h i m p e d a n c e h i g h i m p e d a n c e . . . . . . t x s y n c r x s y n c r x c k . . . . . . . . . . . . u n u s e d o r t x c k . . . . . . b i t c e l l s a t d s t x 0 - 3 c h a n n e l 3 1 b i t 0 c h a n n e l 0 b i t 7 c h a n n e l 0 b i t 6 c h a n n e l 2 3 b i t 0 c h a n n e l 2 4 b i t 7 4 . 2 . 1 . 2 d e t a i l e d s t - b u s g r o u p e d m a p p i n g ( 2 4 c o n s e c u t i v e c h a n n e l s ) i n t h i s o p t i o n , t h e 2 4 b y t e s o f s e r i a l v o i c e / d a t a c h a n n e l s o f t h e d s - 1 u s e t h e r s t 2 4 c o n s e c u t i v e c h a n n e l s o v e r t h e 3 2 s t - b u s c h a n n e l s . t h e m t 9 0 2 2 1 t r i - s t a t e s t h e d s t o l i n e s f o r t h e u n u s e d c h a n n e l s ( 2 5 - 3 1 ) . r e f e r t o t a b l e 9 . 4 . 2 . 1 . 3 d e t a i l e d s t - b u s i s d n m a p p i n g ( t 1 i s d n m o d e s ) w h e n t h e t 1 i s d n m o d e s a r e s e l e c t e d , c h a n n e l 2 4 i s n o t u s e d t o c a r r y b y t e s f r o m a t m c e l l s . t h i s b y t e i s n o t u s e d i n t h e r e c e i v e d i r e c t i o n . i n t h e t r a n s m i t d i r e c t i o n i t i s s e t t o a h i g h i m p e d a n c e s t a t e . t h e s t - b u s m a p p i n g i s i d e n t i c a l a s i n t h e t 1 ( d s 1 ) c l e a r c h a n n e l s e t - u p e x c e p t f o r t h e l a s t c h a n n e l o f t h e t 1 ( d s 1 ) f r a m e . t h i s l a s t c h a n n e l i s r e s e r v e d f o r s i g n a l i n g . 4 . 2 . 2 m o d e 4 a n d 8 : s t - b u s l n t e r f a c e f o r e 1 3 1 . t h e p c m - 3 0 p a y l o a d i s m a p p e d t o 3 0 o f t h e 3 2 s t - b u s t i m e s l o t s . c h a n n e l s 0 a n d 1 6 a r e u s e d f o r f r a m i n g a n d s i g n a l i n g i n f o r m a t i o n . s e e f i g u r e 1 1 a n d t a b l e 1 0 . v a l u e i s 4 . 0 9 6 m h z . t h e f r a m e p u l s e i s 8 k h z a n d s h o u l d b e a s d e n e d i n f i g u r e 1 1 . i n p c m m o d e 4 , t h e t x c k a n d t x s y n c p i n s a r e d e n e d a s i n p u t s a n d a r e g e n e r a t e d b y e x t e r n a l c i r c u i t r y . i n t h e p c m m o d e 8 , t h e t x c k a n d t x s y n c p i n s a r e d e n e d a s o u t p u t s . t h e s o u r c e f o r t h e t x c k i s s e l e c t e d u s i n g t x p c m l i n k c o n t r o l r e g i s t e r n u m b e r 2 a n d c a n b e a n y o f t h e f o u r r x c k t h e z a r l i n k s t - b u s h a s 3 2 c h a n n e l s , n u m b e r e d 0 t o i n e 1 p c m m o d e s 4 a n d 8 , t h e z a r l i n k s t - b u s c l o c k
MT90221 27 figure 11 - pcm mode 4 and 8: st-bus interface for e1 table 10 - channel mapping from st-bus to e1 e1 time-slots - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 voice/data channels (dsti/o) 0 x 1 2 3 4 5 6 7 8 9 101112131415 e1 time-slots - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 voice/data channels (dsti/o) 16 x 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 serial bit stream bit cell bit cell ... ... high impedance high impedance unused or st-bus bit cells (dstx0-3) channel 31 bit 0 channel 0 bit 7 txsync rxsync txck rxck channel 0 bit 0 channel 1 bit 7 ... ... ... ... ... ... st-bus bit cells (dstx0-3) channel 15 bit 0 channel 16 bit 7 serial bit stream bit cell txsync rxsync txck rxck channel 16 bit 0 channel 17 bit 7 bit cell ... ... ... ... ... ... ... ... unused or unused or high impedance unused or high impedance or four external refck clocks. as there is no pll inside the MT90221, the source frequency has to be a valid st-bus clock signal (i.e., 4.096 mhz). the txsync signal is generated by the MT90221 and meets the st-bus format. it is not synchronized with any other rxsync or txsync signal. 4.2.3 mode 1 and 5: generic pcm interface for t1 in pcm modes 1 and 5, the txck clock frequency can be either 1.544 or 2.048 mhz. in the pcm mode 1, the txck and txsync pins are outputs. in the pcm mode 5, the txck and txsync pins are de?ned as inputs. 4.2.3.1 1.544 mhz clock in this sub-mode, (selected by clearing the bit 4 of the tx pcm control register 1,) the serial pcm interface rate is equal to the line bit rate. when selected to operate in this sub-mode, the interface clock is 1.544 mhz and the dsto and dsti the data lines transport only 24 time-slots plus the ds1 framing bit for a total of 193 bits per frame. the frequency value for txsync and rxsync is 8 khz. the frequency for the txck and rxck is 1.544 mhz. the edge of the rxck and txck signals used to sample incoming data and transmit the outgoing data is fully programmable on a per link basis. this allows the MT90221 to operate with the majority of available off-the-shelf t1 framers. when operating in the generic pcm system interface at 1.544 mhz, the MT90221 does not use the ?rst bit of the pcm frame (i.e., the t1 framing bit) to perform the g.804 recommended transmission convergence function (see figure 12). this frame bit is also ignored on the receive side. the position of the frame bit is indicated by the txsync and rxsync signals. 4.2.3.2 2.048 mhz clock in this sub-mode (selected by setting the bit 4 of the tx pcm control register 1) the channel/timeslot mapping for this mode is similar to the st-bus mode for t1. the same pcm mapping schemes (grouped
MT90221 28 figure 12 - mode 1 and 5: generic pcm interface for t1 t1 frame bit cells at dstx0-3 bit 193 bit 1 bit 2 ... serial bit stream bit cell ... bit cell txsync rxsync txck rxck ... ... ... unused or high impedance or spaced) are supported. the txclk and rxclk are 2.048 mhz signal and the txsync and rxsync are a frame pulse of one full bit duration that occurs at the beginning of the frame. the frame rate is 8 khz. the polarity of the txck, rxck, txsync and rxsync and their active edge is programmable using tx pcm link control register number 1 and rx pcm link control register. 4.2.4 mode 3 and 7: generic pcm interface for e1 the channel/timeslot mapping in this mode is similar to the st-bus mode for e1. the differences are: ? the interface clocks (rxck and txck) operate at 2.048 mhz only ? the synchronization signals (txsync and rxsync) are valid for one clock cycle (488 nsec) during the ?rst bit of the frame ? in pcm mode 3, the txck and txsync pins are de?ned as outputs. ? in pcm mode 7, the txck and txsync are de?ned as inputs. the edge of the rxck and txck signals that is used to sample the incoming, and transmit the outgoing, data is fully programmable on a per link basis. this allows the MT90221 to operate with the majority of off-the-shelf e1 framers. the MT90221 does not use timeslots 0 and 16 to perform the g.804 transmission convergence function (see figure 13). 4.2.5 txsync signal in mode 5 and 7 the txsync signal is de?ned as an input in pcm mode 5 and 7 and is sampled at the bit boundary. a positive delay of 10 nsec is expected between the txclk signal at the bit boundary and the time the txsync changes this may cause some inter- operability problems when the mt90220 is connected to some off-the-shelf framers as the txsync can be slightly ahead of the txclk signal. in this case, the txsync signal need to be delayed to ensure proper operation of the tx pcm port. 4.3 clocking options in pcm modes 2, 4, 5 and 7, the txck and txsync are inputs and are generated by external circuitry. in pcm modes 1, 3, 6 and 8, the txck and txsync are outputs. txck source is software selectable and can be any of the four rxck signals or four external refck inputs (see figure 14). the txsync is generated from the txck signal. the rxck pins are always de?ned as inputs and the proper signal must be provided to each input. 4.3.1 verification of the rxsync period the rxsync signal is used to align the incoming dsti data to retrieve all the t1 or e1 channels. the rxsync pulse can be present for each pcm frame (8khz) or once per superframe (every 12 or 24 pcm frames). the period and position of the rxsync is verified for each receive block independently. a status bit (1 per link) in the rx sync status register is set if the synchronization pulse occurs at an unexpected time in the frame. the rx block will be re-aligned with this new synchronization pulse. 4.3.2 verification of the txsync period the txsync signal is used to align the outgoing dsto data to retrieve all the t1 or e1 channels. when de?ned as input, the txsync pulse can be present for each pcm frame (8khz) or once per superframe (every 12 or 24 pcm frames). the
MT90221 29 figure 13 - mode 3 and 7: generic pcm interface for e1 figure 14 - txck and txsync output pin source options st-bus bit cells (dstx0-3) channel 31 bit 0 channel 0 bit 7 serial bit stream bit cell txsync rxsync channel 0 bit 0 channel 1 bit 7 bit cell ... ... ... ... ... ... ... st-bus bit cells at dstx0-3 channel 15 bit 0 channel 16 bit 7 serial bit stream bit cell channel 16 bit 0 channel 17 bit 7 bit cell ... ... ... ... ... ... txck rxck ... ... ... ... ... ... txsync rxsync ... ... txck rxck unused or high impedance unused or high impedance unused or high impedance unused or high impedance ... ... rxck 0-3 pllref0 pllref1 cell delineation s/p p/s tx cell fifo dsto txck txsync dsti rxck rxsync rxck 0-3 refck 0-3
MT90221 30 period and position of the txsync is veri?ed for each transmit block independently. a status bit (1 per link) in the tx sync status register is set if the synchronization pulse occurs at an unexpected time in the frame. the tx block will be re-aligned with this new synchronization pulse. 4.3.3 primary and secondary reference signals two output pins are provided to simplify the external circuitry required when using an external pll. these two pins, pllref0 and pllref1, re-route any of the four rxck signals and drive the primary and secondary reference signals of a pll under software control. refer to section 8, application notes, for examples. 4.3.4 verification of clock activity the MT90221 implements circuitry to determine whether or not a selected clock signal is active. this feature is used to ensure a clock is operational before using it as a source for one or more transmit links. the identity of the clock source to be veri?ed is written to the clock activity register. a read of the same register indicates clock activity if bit 7 is 1. a value of 0 for bit 7 means that no transition was observed on this clock. this circuitry does not measure the frequency of a clock signal, it only detects activity on the four rxck, four txck and four refck signals. 4.3.5 clock selection in normal operation, the clock selection circuitry selects the desired clock signal and ensures a smooth, glitch free, transition between the current clock source and the new clock source. however, if the current clock source is inactive (i.e., no clock transitions), the clock select circuitry must be reset before another clock can be used as reference. clock select circuitry is reset by writing a 1 to bit 7 of the pll reference control register. clock source activity can be veri?ed using the clock activity register as described in 4.3.4 veri?cation of clock activity. 5.0 utopia interface operation the MT90221 supports the utopia l2 mode for cell level handshake only. each port can be assigned an address ranging from 0 to 30. the address value of 31 is reserved and should not be used for any MT90221 port. the tx and rx paths of each ima group and each link in uni has its own phy address. these phy addresses are de?ned in the utopia input link address registers 1 to 4, utopia input group address register 1 to 4, utopia output link address registers 1 to 4, and the utopia output group address registers 1 to 4. the utopia input link phy enable and the utopia output link phy enable registers are used to enable the phy address of the links in uni. the utopia input group phy enable register and the utopia output group phy enable registers are used to enable the phy address of the ima groups. the MT90221 port uses handshaking signals to process data streams. the start of a cell (soc) is marked by the utopia soc sync signal. this signal is active during the transfer of the ?rst byte of a cell. the 52 bytes that follow the arrival of the ?rst byte of a cell are interpreted as belonging to the same cell and are stored accordingly (note that soc sync signals received during the loading of these 52 bytes are ignored). the cell available satus line (clav) is used to communicate to the atm controller if the mt90220 has space for a cell in the phy address that was polled in the previous cycle. whenever there is space for a cell in teh tx direction or a cell ready in the rx direction, the txclav and/or rxclav signal will be driven high or low. when the address does not correspond to any enabled phy address inside the mt90220, the txclav and rxclav signal are in high impedance mode. the use of an external pull- down may be required for the proper operation of the utopia bus. it should be noted that the bit 6 and 5 of the test 1 register have to be set to 1 for the proper operation of the rx utopia port in mphy mode. 5.1 atm input port the utopia interface input clock txclk is independent of the system clock. the utopia txclk can be up to 25mhz. the incoming cell is stored directly in the internal tx cell ram where the tx utopia fifos are implemented. the tx byte clock (txclk) can be up to 25 mhz and is checked against the system clock. if the incoming byte clock frequency is lower than 1/128 of the system clock, bit 2 of the general status register will be set. this bit is cleared by overwriting it with 0. the total space for the utopia input cells for all ima groups and links in uni mode is 58. these 58 cells are shared between 8 tx utopia fifos and 4 tx link fifos. the size (length) of each tx utopia fifo is de?ned by writing to the tx utopia fifo length de?nition registers. the maximum value is
MT90221 31 15 and the minimum value is 0 (in the case the phy port is not to be used). the size of the tx link fifo is de?ned on a per group using the tx ima control registers. the device will not accept a cell from the utopia interface if the internal cell ram is full. status bit 0 in the general status register is set to 1 to indicate the no free cell in tx cell ram condition. the status bit can be cleared by overwriting it with 0. the utopia input block has the option to verify the hec of the cell coming from the atm layer. four different options are available and are selected by bit 1 and 0 of the utopia input control register. ? the 00 option is used to always accept a cell from the atm layer. the hec is veri?ed and if wrong, the utopia input counter associated with the utopia port for cells with bad hec is incremented. the MT90221 will re-generate a valid hec based on the content of the 4-byte header that was received. ? the 01 option is used to verify the hec of an incoming cell. if the hec value is wrong and if it can be corrected (1 bit error), then the cell is corrected and accepted as a good cell. the bad hec counter is not incremented if the hec is corrected. the bad hec counter is incremented if the hec value cannot be corrected. in this mode, the cell is always accepted. the MT90221 will re-generate a valid hec based on the content of the 4-byte header that was received. ? the 10 option is used to verify the hec on the incoming cell and discard the cell if the hec value is wrong. the bad hec counter is incremented if a cell is discarded. ? the 11 option is similar to mode 01 except that if the hec value cannot be corrected, then the cell is discarded. if the hec value is corrected, the bad hec counter is not incremented. 5.2 atm output port the MT90221 supports a 53 byte cell stream via the atm output port. cells received at the atm output port are stored in the rx utopia fifo before being processed by the utopia interface. the output of the utopia interface can be stopped by the atm layer device by de-asserting the rxenb* signal. the start of a cell is marked with the soc signal, which is active during the transmission of the ?rst byte of a cell. the following 52 bytes are expected to belong to the same cell. the rx byte clock (rxclk) can be up to 25 mhz and is checked against the system clock. if the incoming byte clock frequency is lower than 1/128 of the system clock, bit 3 of the general status register will be set. this bit is cleared by overwriting it with 0.the rxclk signal has to be synchronized with the system clock for the proper operation of the mt90220. typically, both frequencies are equal but the rxclk frequency can be lower. over?ow conditions in the rx utopia fifo associated with any of the 8 phy rx addresses cause a status bit to be set in either the irq utopia uni over?ow status or irq ima group over?ow status register. these status bits are cleared by overwriting them with 0. additionally, for each status bit there is an interrupt enable bit in the associated rx utopia link fifo over?ow enable or rx utopia ima group fifo over?ow enable register. when enabled, the status bit is reported in an interrupt register. see 6.2 interrupt block for more details. the size of the rx utopia fifo is ?xed at two cells for the uni phy addresses and four cells for the ima group phy addresses. 5.3 utopia operation with a single phy a single atm layer device with a utopia l2 mphy port can be connected to the atm input port of one MT90221. another atm-layer device using the utopia l2 mphy input interface is used to receive atm cells from the MT90221. the address pins should be set to the value programmed by the management interface. in this mode, the bit 6 and 5 of the test 1 register are not to be set to 1 for the proper operation of the rx utopia port. 5.4 utopia operation with multiple phy when more than one MT90221 are connected to a single atm layer device the single txclav and rxclav scheme is used. direct status indication and multiplexed status polling schemes are not supported. the necessary polling is performed by the atm-layer device. the utopia interface transmit and receive addresses, provided by the atm-layer device, are used to de-multiplex the atm-cell stream to as many as eight MT90221s. the maximum available bandwidth for four e1 lines served by each MT90221 device is 2 mbytes/s.
MT90221 32 5.5 utopia operation in uni mode in uni mode, each utopia port inside an MT90221 corresponds to a physical t1 or e1 line. up to eight phy ports can be supported by one MT90221. up to eight MT90221 can be connected to a utopia bus. the ports in the same device represent only one electrical load on the utopia bus. the utopia interface supports up to 31 phy addresses so a maximum of 31 phy addresses are supported by the MT90221. the mphy address at the input port of MT90221 (txaddr[4:0]) is used to store the cell in one speci?c tx utopia fifo. the mphy address at the output port (rxaddr[4:0]) is used to retrieve the cells from the proper rx utopia fifo. 5.6 utopia operation in ima mode in ima mode, up to eight MT90221s, with up to four utopia ports each (one port per ima group), can be served by an external utopia l2 atm-layer device. this provides up to 31 different logical ima- channels. note that port 31 (1f in hexadecimal format) is reserved. 5.7 examples of utopia operation modes figure 15 shows the connection of one atm device with one MT90221. figure 15 - atm interface to MT90221 figure 16 shows the connection of one atm device with more than one MT90221. figure 17 illustrates the implementation of a mixed mode using only 1 MT90221. links that are not used for ima groups are available in uni mode. unused links are programmed to set their outputs to high impedance mode. txclk txaddr txdata rxenb* rxclav rxsoc txclav txsoc rxdata rxclk rxaddr atm txenb* MT90221 atm layer physical layer framer framer . . . . . figure 16 - atm interface to multiple MT90221s atm txclk txenb* txaddr txclav txsoc txdata rxclk rxenb* rxaddr rxclav rxsoc rxdata MT90221 framer framer atm layer physical layer txclk txenb* txaddr txclav txsoc txdata rxclk rxenb* rxaddr rxclav rxsoc rxdata MT90221 framer framer
MT90221 33 6.0 support blocks 6.1 counter block the MT90221 includes 64 24-bit counters to provide statistical information on the devices operation. all the counters are cleared by a hardware reset. a maskable interrupt can be generated when the counter over?ows. a predetermined value can also be loaded in a counter. this feature can be used to generate an interrupt after a speci?ed number of cells is processed. counter values are incremented by 1 for every event occurrence and, when the count goes to all 1s, will over?ow (to all 0s). 6.1.1 utopia input i/f counters there are four counters associated with the each of the 8 utopia inputs (from atm layer to the MT90221) for a total of 32 counters. these counters record the following information: ? the total number of cells received at the utopia input i/f ? the total number of idle cells received at the utopia input i/f, removed or not ? the total number of unassigned cells received at the utopia input i/f, removed or not ? the number of cells having a single or multiple bit error in the hec, removed or not but not including the cells where the hec is corrected 6.1.2 transmit pcm i/f counters there are four counters associated with the each of the four transmit pcm links for a total of 16 transmit counters. these counters record the following information and are active as soon as the rx pcm port is enabled: ? the total number of cells sent through the pcm link ? the total number of idle/filler cells sent through the pcm link, with good or bad hec ? the total number of stuff cells sent through the pcm link ? the total number of icp cells sent through the pcm link 6.1.3 receive pcm i/f counters there are four counters associated with each of the four receive pcm links for a total of 16 receive counters. these counters record the following information: ? the total number of cells received through the pcm link or total number of stuff events received on the link (option selected in rx link control registers) ? the total number of idle/filler cells received through the pcm link ? the total number of icp cells with violation received through the pcm link ? the total number of cells with wrong hec received through the pcm link but not including the cells where the hec is corrected 6.1.4 access to the counters accessing (read) counters is a three step function. first, the desired counter must be selected by writing to the counter select register . second, the read command (0x00x101) is written to the counter transfer command register. this command causes the current three byte count value to be copied from the speci?ed counter to the three byte-wide counter bytes registers (note that this value is unchanged until another counter read command is issued). and third, the counter bytes registers are read to obtain the three byte count value of the selected counter. pre-loading (write) a counter is also a three step function. first, the three byte, pre-load value, is written to the three byte-wide counter bytes registers. second, the identi?cation of the counter to be pre-loaded is written to the counter select register . and third, the write command (0x00x001) is written to the counter transfer command register. the irq enable bit of a counter is set, or reset, by selecting the counter and writing to the appropriate figure 17 - atm mixed-mode interface to one MT90221 (ima group #1) (2 links in uni mode) atm 2 utopia ports (uni) 4 layer device framer 1 utopia port (2 links)
MT90221 34 bit of the counter transfer command register. the value 0x001010 enables the counter irq and xxx00010 disables (masks) it. 6.2 interrupt block the MT90221 can generate interrupts from many sources. all interrupt sources can be enabled or disabled. write action is required to clear the source of interrupt. interrupts are grouped on a per link basis, with six sub-categories for each link and two special types for the ima group con?guration. these special interrupts are only present in the link 0 irq status register. refer to figure 18 for a representation of the interrupt register hierarchy. 6.2.1 irq master status and irq master enable registers there is a master irq status register that reports interrupts generated by any event on any of the eight links. each bit of this register corresponds to a link. a 1 in a bit position indicates that the associated link is reporting an interrupt condition. for each bit in the irq master status register, there is a corresponding bit in the irq master enable register. when any irq source is active and the corresponding enable bit is 1, then the irq pin will go low (active). the irq master status register always reports the current state of the source(s) of interrupt. it does not latch the interrupt request(s); it only reports that one or more bit(s) in one or more irq link status register(s) is (are) set. the bits that are read as active (1 value) are cleared when the source of the interrupt is cleared or when the corresponding bit(s) in the irq link enable register(s) is (are) set to 0. writing to or reading from the irq master status register has no effect on the level of the interrupt pin. 6.2.2 irq link status and irq link enable registers there are four irq link status and four irq link enable registers; one of each per link. the following figure 18 - irq register hierarchy s t a t u s group counters utopia ima link 3 link 2 link 1 link 0 link 3 irq pin link 0 lcd lif lods iv new rx icp link uni overflow status counters counters 4 tx 4 rx s t a t u s counters 4 utopia s t a t u s s t a t u s ready bit/icp cell time * note * : these 2 irq signals are only present in irq status register for link 0. 1 utopia rx fifo overflow ima group overflow ima overflow 1 set of registers 4 registers counters 4 utopia 1 utopia rx fifo overflow frame pulse transfer done tx icp cell handler register s t a t u s s t a t u s 4 x irq link registers 1 x irq master registers ima grp cntrs * e n a b l e e n a b l e e n a b l e e n a b l e 0 7
MT90221 35 six types of interrupts are reported (in the six least signi?cant bits of the irq link status registers) for each link: ? bit 5 latched: reports that an icp cell with changes was received on a rx pcm link. ? bit 4 latched: reports an iv (icp cell violation) condition on a rx pcm link. ? bit 3 latched: reports an lods (link is out of delay synchronization) condition on a rx pcm link. ? bit 2 latched: reports an lif (loss of ima frame) condition on a rx pcm link. ? bit 1 latched: reports an lcd (loss of cell delineation) condition on a rx pcm link. bit 0 (lsb) is a status bit. it reports an interrupt for an over?ow condition in one or more of the 12 counters associated with the link. it is also used to report an over?ow condition in the utopia rx fifo associated with a pcm link in uni mode. if enabled, a counter generates an interrupt request when it over?ows (i.e starts over from 0 after reaching the maximum counter value). 6.1 counter block paragraph for more details on the operation of the counters. these 13 sources of over?ow can be identi?ed through the irq link fifo over?ow and irq utopia fifo over?ow status registers. refer to section 6.2.3 irq link uni over?ow and irq utopia input uni over?ow status registers for more details. reading the irq link status register does not clear the source of interrupt. the bit 0 status is reset by any one of the following procedures: ? disabling (masking) the irq for this speci?c counter ? clearing the over?ow status bit in the irq link uni overflow and irq utopia uni overflow status registers ? disabling the interrupt in the rx utopia link fifo over?ow enable or in the corresponding link (in uni mode) counter registers. bits 1, 2, 3, 4 and 5 of the irq link status register are latches that report the source of an interrupt. writing a 0 these bits will reset the status bit (will reset the latch). writing 0 to bit 0 has no effect on the status bit. writing a 1 has no effect on the bits 0 to 5 of the irq link status register. each one of these six interrupt sources can be enabled by writing a 1 in the irq link enable register to the bit corresponding to the interrupt source. in some situations, an interrupt source can be masked as part of an interrupt service routine. this makes it possible to detect further interrupts of higher priority. for example, if an interrupt for a counter is received, the source of the interrupt can be masked by writing 0 to the bit 0 and then starting a separate process, outside of the interrupt service routine. the independent process would read, reload and re-enable the counter to produce another interrupt service request, if necessary. at the end of this process, the enable bit in the irq link enable register would be set to 1 to detect any future interrupt requests. 6.2.2.1 bit 7 and 6 of irq link 0 status and irq link 0 enable registers bits 7 (msb) and 6 of the irq link 0 status register have a special meaning. bit 7 reports an over?ow condition in any of the counters or utopia rx fifos associated with one of the four ima groups. refer to 6.2.4 irq ima group over?ow status and enable registers for more details. bit 7 is a status bit and is cleared by disabling the irq for this speci?c counter or disabling (masking) the fifo over?ow condition by writing to the rx utopia ima group fifo over?ow enable register. bit 6 is used to report the following two event types: ? the icp cell internal transfer is complete (reported by any ima group tx icp cell ready bit) ? the end of an ima frame on the reference link of an ima group the second type of event assists in implementing the software counter required to verify that group status and control ?eld information is sent for at least 2 consecutive ima frames. the eight interrupt sources are enabled independently by writing to the tx icp cell handler enable register. there is also an associated control/status register ( tx icp cell handler register) that reports the interrupt source and the state of the transfer of an icp cell or the occurrence of the end of an ima frame. the frame status bits are cleared by writing 0 to the bit. the ready bit is set to 1 when the transfer is complete. bit 6 is a latched bit in the irq link 0 status register and is cleared by overwriting it with 0. each of these two interrupt sources can be masked by writing a 1 to the bit corresponding to the interrupt source in the irq link 0 enable register.
MT90221 36 6.2.3 irq link uni overflow and irq utopia input uni overflow status registers the irq link uni over?ow and the irq utopia input uni over?ow status registers report the over?ow condition from any of the counters associated with the tx pcm link, the rx pcm link or the tx utopia i/f. they also report the over?ow condition from the level of the utopia rx fifo when the link is used in uni mode. the 13 interrupt sources are organized in the following two registers: ? an 8-bit register that reports the over?ow condition from the eight counters associated with a tx or rx pcm link (the irq link uni overflow status registers) ? a 5-bit register that reports the over?ow condition from the four counters associated with the utopia tx i/f to the pcm link used in uni mode as well as an over?ow condition from the rx utopia fifo associated to a rx pcm link when in uni mode (the irq utopia input uni overflow status registers) the ?ve bits in the irq utopia input uni over?ow status registers are latched to report an over?ow condition. the status bit is cleared by overwriting it with a 0. reading the registers or writing a 1 to these registers will not change the content of the registers. there is no enable register directly associated to the irq link uni over?ow status registers. the source of the interrupt request can be controlled either by enabling the interrupt from the counters or from the rx utopia link fifo over?ow enable register. refer to 6.1 counter block paragraph for more details on the operation of the counters. 6.2.4 irq ima group overflow status and enable registers there are 20 sources of ima group over?ow conditions organized in two levels of registers: ? four low level, 5-bit registers (one register per ima group) ? one intermediate 4-bit register that is used to report the over?ow conditions for each ima group to minimize the number of accesses to identify the source of an over?ow condition the irq ima group over?ow status register indicates which one of the four ima groups is reporting an over?ow condition. when enabled, the bits in this status register re?ect any over?ow condition reported by the irq ima over?ow status registers. the irq ima group over?ow enable register is used to enable any over?ow conditions for a speci?c ima group. each of the four bits correspond to one of the four ima groups. a value of 1 enables the report of the over?ow condition to the upper irq levels. 6.2.5 irq ima overflow status and rx utopia ima group fifo overflow enable registers there are ?ve possible sources of over?ow conditions that can be reported for each of the 4 ima groups. the irq ima over?ow status register captures (latches) the over?ow condition from any of the four counters associated with the utopia tx i/f when the pcm link is used in ima mode. it also latches when an over?ow condition occurs in the rx utopia fifo associated to a pcm link when in ima mode. the status bit is cleared by overwriting it with a 0. reading the registers or writing a 1 to these registers will not change the content of the registers. a counter generates an interrupt request, if not masked, when the counter over?ows (i.e. starts over from 0 after reaching the maximum counter value - refer to paragraph 6.1 for more details on the operation of the counters). an interrupt request can also be generated, if not masked, when an over?ow condition is detected in the utopia rx fifo associated with an ima group. there is one enable register used to enable the generation of an interrupt by the over?ow condition of the rx utopia fifo associated with an ima group. this is the rx utopia ima group fifo over?ow enable register. 6.3 register and memory map 6.3.1 access to the various registers since the MT90221 and microprocessor operate from two different clock sources, access to a MT90221 register is asynchronous. data is synchronized between the MT90221 and the microprocessor using either direct or indirect (synchronized) methods of access. the direct method is used during a read access whenever data does not change or data changes do not represent any problem. there is no register that clears status bits upon a read access. a write action is always required to clear a status bit. the indirect method is identi?ed with s (indirect and need to synchronize with a ready bit) whereas the direct access is identi?ed with a d in the register tables.
MT90221 37 6.3.2 direct access direct access registers can be written or read directly by the microprocessor, without having to use otherregisters. upon a write access to the MT90221 internal registers, the data is stored in an internal latch and transferred to the destination register within 2.5 system clock cycles (100 nsec at 25 mhz). no speci?c action is required if the microprocessor provides at least 100 nsec (with chip select signal inactive) between 2 consecutive write accesses or between a write and a read back of the same register. if the microprocessor is faster, then consecutive accesses must be inhibited or wait state(s) introduced (this option is available on most mcus). 6.3.3 indirect access indirect access registers cannot be accessed directly by the microprocessor. the value is transferred back and forth using registers which hold a copy of the information (data) and internal address of the register. this is required to stabilize the read value. consider for example the transfer of a tx icp cell that requires almost 200 system clock cycles. a dedicated ready bit which can optionally generate an interrupt is implemented for this type of transfer. accessing any of the 24 bit counters provides another example. a ready bit is implemented in the counter transfer command register when the transfer is completed. when accessing indirect registers speci?ed by the rx delay select or rx load values/link select registers, the value in the indirect registers can be read when the write to the selection register is effectively done (i.e. 2.5 system clock cycles after the write cycle is completed). there is no additional delay required. 6.3.4 clearing of status bits the status bits will remain set until cleared by a speci?c write action from the microprocessor. status bits are cleared by overwriting a zero to the corresponding position in the source register. each input status register has a related interrupt enable register. when enabled, setting a bit in the interrupt enable register causes an interrupt to occur in the corresponding status register bit. 6.3.4.1 toggle bit some registers include a toggle bit. toggle bits are used to indicate a write action to any internal register has taken place. typically, this bit is toggled 2.5 system clock cycles after performing the write action. to use the toggle bit, its state (either 0 or 1) must be read (polled) and its state is changed (toggled) when a write command is completed. this bit is particularly useful when the processor clock is much faster than the MT90221 system clock. 6.3.5 test modes access is provided to the external sram from the microprocessor using a special test mode and test registers (i.e., to assist in debugging or veri?cation). the test mode is enabled by writing to bit 7 of the test mode enable register, writing 0x10 to the rx delay link number register and by writing 0x29 to the rx external sram control register. indirect access is provided using the rx external sram read/write data register for the data to be written or read and the rx sram external address 0 , 1 and 2 registers for the address of the sram location. the write transfer command is issued using the rx external sram control register. bit 7 of the rx external sram control is cleared (set to 0) and then returned to 1 when the write action is completed. please note that during normal operation, the microprocessor access to the external sram should be disabled. this is done by writing 0x00 to the rx delay link number register.
MT90221 38 7.0 register descriptions address (hex) access type reset value (hex) table # description 000 - 003 d 00 12 utopia input link address registers 008 - 00b d 00 13 utopia input group address registers 00c d 00 14 utopia input link phy enable register 00d d 00 15 utopia input group phy enable register 00e d 00 16 utopia input control register. 040 - 043 d 00 17 utopia output link address registers 048 - 04b d 00 18 utopia output group address registers 04c d 00 19 utopia output link phy enable register 04d d 00 20 utopia output group phy enable register 205 d 00 21 rx utopia ima group fifo over?ow enable register 221 d 00 22 rx utopia link fifo over?ow enable register 140 d 00 23 tx cell ram control register 150 d 00 24 tx utopia fifo level 14a d 33 25 tx fifo length de?nition register 1 14b d 33 26 tx fifo length de?nition register 2 14c d 33 27 tx fifo length de?nition register 3 14d d 33 28 tx fifo length de?nition register 4 14e d 33 29 tx fifo length de?nition register 5 14f d 33 30 tx fifo length de?nition register 6 0c0 - 0c3 d 58 31 tx group control mode register 0dd - 0e0 d link # 32 tx link id registers 0c4 - 0c7 d link # 33 tx icp cell offset registers 200 - 203 d 05 34 tx idcr integration registers 0cc - 0cf d 04 35 tx link control registers 0d4-0d7 d 29 36 tx ima control register 0ef d 00 37 tx ima mode status register 148 d 0f 38 tx icp cell handler register 149 d 00 39 tx icp cell interrupt enable register 300, 340, 380, 3c0 d see table 40 tx icp cell registers (access to icp cell bytes) 100 - 103 d 0c 41 rx link control registers 109 d 67 42 cell delineation register 108 d 0c 43 loss cell delineation register 10a d 91 44 ima frame de?nition register 10c - 10f d 01 45 rx oam label 115 d 00 46 rx oif status register 116 d 00 47 rx oif counter clear command register 117 d 00 48 rx load values/link select register 118 d 00 49 rx link ima id registers table 11 - register summary
MT90221 39 119 d 00 50 rx icp cell offset register 11a d 00 51 rx link frame sequence number registers 11b d 00 52 rx link scci sequence number registers 11c d 00 53 rx link oif counter value register 11d d 20 54 rx link id number registers 11e d 00 55 rx state register 1c0 d 00 56 rx icp cell type ram register 1 1c6 d 00 57 rx icp cell buffer increment read pointer register 1c7 d 00 58 rx icp cell level fifo status register 1c3 s 00 59 test mode enable register 292 d 08 60 sram control register 283 s 00 61 rx external sram read/write data 291 s 00 62 rx external sram read/write address 0 290 s 00 63 rx external sram read/write address 1 28f s 00 64 rx external sram read/write address 2 280 s 80 65 rx external sram control register 281 d 00 66 increment/decrement delay control register 29d d 00 67 rx delay select register 284 d 00 68 rx delay msb register 285 d 04 69 rx delay lsb register 286 d 00 70 rx delay link number register 288, 28a, 28c, 28e d 04 71 rx guardband/delta delay lsb register, 1 per ima group 287, 289, 28b, 28d d 00 72 rx guardband/delta delay msb register, 1per ima group. 296, 298, 29a, 29c d 00 73 rx maximum operational delay lsb register, 1 per ima group. 295, 297, 299, 29b d 00 74 rx maximum operational delay msb register 180 - 183 d 00 75 rx recombiner registers 282 d 00 76 rx recombiner delay control register 29f d 00 77 enable recombination status 188 - 18b d 00 78 rx reference link control registers 18c - 18f d 05 79 rx idcr integration register 080 - 083 d 00 80 tx pcm link control register #2 088 - 08b d 00 81 tx pcm link control register #1 090 - 093 d 00 82 rx pcm link control register 098 d 00 83 pll reference control register 099 d 00 84 clock activity register 09a d 00 85 rx sync. status register 09e d 00 86 tx sync. status register address (hex) access type reset value (hex) table # description table 11 - register summary
MT90221 40 09c d 00 87 tx clock disabled status 09d d 10 88 pll ref clock disabled status/device rev. 214 s 00 89 counter byte #3 register 215 s 00 90 counter byte #2 register 216 s 00 91 counter byte #1 register 217 s 00 92 select counter register 207 s 00 93 counter transfer command register 232 d 00 94 irq master status register 218 d 00 95 irq master enable register 222 - 225 d 00 96 irq link status registers 219 - 21c d 00 97 irq link enable registers 235 d 00 98 irq ima group over?ow status register 204 d 00 99 irq ima group over?ow enable register 210 - 213 d 00 100 irq ima over?ow status registers 208 - 20b d 00 101 irq utopia uni over?ow status registers 22a - 22d d 00 102 irq link uni over?ow status registers 206 d 00 103 general status register 04e d 00 104 test 1 register 0da d 00 105 test 2 register 400, 440 d 00 base address for the 2 rx icp cell with changes, link 0 480, 4c0 d 00 base address for the 2 rx icp cell with changes, link 1 500, 540 d 00 base address for the 2 rx icp cell with changes, link 2 580, 5c0 d 00 base address for the 2 rx icp cell with changes, link 3 address (hex) access type reset value (hex) table # description table 11 - register summary
MT90221 41 7.1 utopia register description tables 12 to 22 describe the utopia registers. address (hex): 000 - 003 direct access 1 register per link in uni mode. the txclk signal must be active for correct register operation. reset value (hex): 00 bit # type description 7:5 r unused. read all 0s. 4:0 r/w utopia phy address of link n when in uni. table 12- utopia input link address registers address (hex): 008 - 00b direct access 11 reg. per ima group. the txclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7:5 r unused. read all 0s. 4:0 r/w utopia phy address of ima group n. table 13 - utopia input group address registers address (hex): 00c direct access 1 register to enable the links in uni mode. the txclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7-4 r/w reserved.write 0 for normal operation 3 r/w enable utopia phy address of link 3. a 1 enables the phy port address. uni mode. 2 r/w enable utopia phy address of link 2. a 1 enables the phy port address. uni mode. 1 r/w enable utopia phy address of link 1. a 1 enables the phy port address. uni mode. 0 r/w enable utopia phy address of link 0. a 1 enables the phy port address. uni mode. table 14 - utopia input link phy enable register
MT90221 42 a. unassigned cells have a fixed header corresponding to 00000000 00000000 00000000 0000xxx0. b. idle cells have a fixed header corresponding to 00000000 00000000 00000000 00000001 address (hex): 00d direct access 1 register to enable the ima groups. the txclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7-4 r/w reserved. write all 0s . 3 r/w enable utopia phy address of ima group 3. a 1 enables the phy port address. 2 r/w enable utopia phy address of ima group 2. a 1 enables the phy port address. 1 r/w enable utopia phy address of ima group 1. a 1 enables the phy port address. 0 r/w enable utopia phy address of ima group 0. a 1 enables the phy port address. table 15 - utopia input group phy enable register address (hex): 00e direct access 1 register for all the utopia input ports. the txclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7 r reserved. 6 r/w utopia input reset. a 1 will reset the utopia input state machine. all other user programmable registers are not cleared. a 0 is used for normal operation. 5 r/w reserved. write 0. 4 r/w unassigned cell filter. a 1 signi?es that the unassigned a cells coming from the atm layer will be discarded. the unassigned/idle cell counter is incremented for each cell discarded. 3 r/w idle cell filter. a 1 signi?es that the idle b cells coming from the atm layer will be discarded. the unassigned/idle cell counter is incremented for each cell discarded. 2 r/w atm forum polynomial. a 1 disables the addition of the atm forum polynomial calculation on the hec calculated as per i.432. a 0 means that the closest value is included in the hec value. 1-0 r/w hec veri?cation. 11: enable hec error correction if 1 bit is wrong, discard cell if more than 1 bit are wrong. 10: discard cell if hec is wrong, ho hec correction. 01: enable hec error correction if 1 bit is wrong, no correction if more than 1 bit wrong, cell is not discarded if hec is wrong. 00: no veri?cation of hec. table 16 - utopia input control register address (hex): 040 - 043 direct access 1 register per link in uni mode. the rxclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7:5 r unused. read all 0s. 4:0 r/w utopia phy address of link n when in uni (non-ima) mode. table 17 - utopia output link address registers
MT90221 43 address (hex): 048 - 04b direct access 1 reg. per ima group.link. the rxclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7:5 r unused. read all 0s. 4:0 r/w utopia phy address of ima group n. table 18 - utopia output group address registers address (hex): 04c direct access 1 register to enable the links in uni mode. the rxclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7-4 r/w reserved. write 0 for normal operation. 3 r/w enable utopia phy address of link 3. a 1 enables the phy port address. uni mode 2 r/w enable utopia phy address of link 2. a 1 enables the phy port address. uni mode 1 r/w enable utopia phy address of link 1. a 1 enables the phy port address. uni mode 0 r/w enable utopia phy address of link 0. a 1 enables the phy port address. uni mode table 19 - utopia output link phy enable register address (hex): 04d direct access 1 register to enable the ima groups. the rxclk signal must be active for correct register operation reset value (bin): x0000000 bit # type description 7 r watch clock. this bit re?ects the level present on the rx utopia clock pin when this register is read. 6 r/w reserved, write 0 for normal operation. 5 r/w reset utopia rx state machines when set to 1. 4 r/w reserved, write 0 for normal operation. 3 r/w enable utopia phy address of ima group 3. a 1 enables the phy port address. 2 r/w enable utopia phy address of ima group 2. a 1 enables the phy port address. 1 r/w enable utopia phy address of ima group 1. a 1 enables the phy port address. 0 r/w enable utopia phy address of ima group 0. a 1 enables the phy port address. table 20 - utopia output group phy enable register
MT90221 44 address (hex): 205 direct access 1 register to enable interrupts from ima groups. the rxclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7-4 r unused. read all 0s. 3 r/w when set to 1, the corresponding bit in the over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. ima group 3. 2 r/w when set to 1, the corresponding bit in the over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. ima group 2. 1 r/w when set to 1, the corresponding bit in the over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. ima group 1. 0 r/w when set to 1, the corresponding bit in the over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. ima group 0. table 21 - rx utopia ima group fifo over?ow enable register address (hex): 221 direct access 1 register to enable interrupts from the links in uni mode. the rxclk signal must be active for correct register operation reset value (hex): 00 bit # type description 7-4 r/w reserved. write 0 for normal operation. 3 r/w when set to 1, the corresponding bit in the irq utopia uni over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. link3. 2 r/w when set to 1, the corresponding bit in the irq utopia uni over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. link 2. 1 r/w when set to 1, the corresponding bit in the irq utopia uni over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. link 1. 0 r/w when set to 1, the corresponding bit in the irq utopia uni over?ow status register can generate an interrupt. a value of 0 inhibits the generation of an interrupt. link 0. table 22 - rx utopia link fifo over?ow enable register
MT90221 45 7.2 tx registers description tables 23 to 37 describe the transmit registers. address (hex): 140 direct access used for initialization of the tx cell ram (filler, idle cells etc.) reset value (bin): 1x000000 bit # type description 7 r goes to 0 during initialization and returns to 1 on completion of initialization. 6 r/w reserved, write 0 for normal operation. 5 r/w reserved. write 0 for normal operation. 4:1 r/w reserved, write 0s for normal operation. 0 r/w reserved. write 0 to initialize the cell ram. table 23 - tx cell ram control register address (hex): 150 direct access reset value (hex): 00 bit # type description 7:4 w write 0 for normal operation. 3:0 w write 1000 to load the tx utopia fifo level of ima group 0 write 1001 to load the tx utopia fifo level of ima group 1. write 1010 to load the tx utopia fifo level of ima group 2. write 1011 to load the tx utopia fifo level of ima group 3. 7:5 r reserved, read 0s. 4:0 r level of selected fifo. table 24 - tx utopia fifo level register address (hex): 14a direct access reset value (hex): 33 bit # type description 7:4 r/w tx fifo length link 1. 3:0 r/w tx fifo length link 0. table 25 - tx fifo length de?nition register 1 address (hex): 14b direct access reset value (hex): 33 bit # type description 7:4 r/w tx fifo length link 3. 3:0 r/w tx fifo length link 2. table 26 - tx fifo length de?nition register 2
MT90221 46 address (hex): 14c direct access reset value (hex): 33 bit # type description 7:0 r/w reserved. write 0 for normal operation. table 27 - tx fifo length de?nition register 3 address (hex): 14d direct access reset value (hex): 33 bit # type description 7:0 r/w reserved. write 0 for normal operation. table 28 - tx fifo length de?nition register 4 address (hex): 14e direct access reset value (hex): 33 bit # type description 7:4 r/w tx fifo length ima group 1. 3:0 r/w tx fifo length ima group 0. table 29 - tx fifo length de?nition register 5 address (hex): 14f direct access reset value (hex): 33 bit # type description 7:4 r/w tx fifo length ima group 3. 3:0 r/w tx fifo length ima group 2. table 30 - tx fifo length de?nition register 6
MT90221 47 address (hex): 0c0 - 0c3 direct access 1 register per tx ima group reset value (hex): 58 bit # type description 7 r/w reserved, write 0 for normal operation. 6-5 r/w value of m. these 2 bits speci?es the value of m for the ima group. 00: m=32, 01: m=64, 10: m=128 11: m=256 4 r/w timing mode inserted in icp cell. a 0 means that the itc timing mode is inserted in the icp cell and a 1 means that the ctc timing mode is inserted in the icp cell. 3 r/w timing mode in roundrobin scheduler. a 0 means that the itc timing mode (adaptive) algorithm is selected and a 1 means that the ctc timing mode (?xed) algorithm is selected for internal operation. 2 r/w reserved. write 0 for normal operation. 1:0 r/w reference link. these 2 bits de?ne which physical link is to be used as reference for timing purposes. table 31 - tx group control mode registers address (hex): 0dd- 0e0 direct access 1 register per link, used in ima mode only. reset value (hex): 0dd: 00, 0de: 01 0df: 02, 0e0: 03 bit # type description 7:5 r/w reserved, must write 0 for normal operation. 4:0 r/w link id for the link n. the value can be between 0 and 31. this is the logical value associated to a physical link. used in ima mode only. table 32 - tx link id registers address (hex): 0c4 - 0c7 direct access 1 register per link, used in ima mode only reset value (hex): 0c4: 00, 0c5: 01 0c6: 02, 0c7: 03 bit # type description 7:0 r/w de?nes the icp cell offset of link n. the value of m determines which signi?cant bits are used as follows: m=256; bits 7-0 are used, m=128; bits 6-0 are used; m=64; bits 5-0 are used; m=32; bits 4-0 are used. table 33 - tx icp cell offset registers
MT90221 48 address (hex): 200 - 203 direct access 1 register per tx ima group reset value (hex): 05 bit # type description 7:4 r unused. read all 0s. 3-0 r/w de?nes the integration period for an ima group: 1111: reserved. do not use. 1110: 2 21 clock cycles 1101: 2 20 clock cycles 1100: 2 19 clock cycles (preferred value for e1) 1011: 2 18 clock cycles (preferred value for t1 - 24 channels) 1010: 2 17 clock cycles 1001: 2 16 clock cycles (preferred value for t1 - 23 channels) 1000: 2 15 clock cycles 0111: 2 14 clock cycles 0110: 2 13 clock cycles 0101: 2 12 clock cycles 0100: 2 11 clock cycles 0011: 2 10 clock cycles 0010: 2 09 clock cycles 0001: 2 08 clock cycles 0000: 2 07 clock cycles table 34 - tx idcr integration registers address (hex): 0cc - 0cf direct access 1 register per link reset value (hex): 04 bit # type description 7 r/w reserved, write 0 for normal operation. 6 r/w set to 1 to start sending user cells in ima mode. set to 0 to send always filler and icp cells in ima mode (note: in uni mode, the control to send user cells is implemented with the utopia input link phy enable register). 5 r/w coset value. a 0 will generate hec with coset value, when 1, coset is not added. 4 r/w cell scrambling. a 1 enables the scrambling of the cells on the link n. 3 r/w reserved, must write a 0 for normal operation. 2 r/w set to 1 for uni mode and clear to 0 for ima mode. select the ima group number before enabling the ima mode. 1:0 r/w de?nes ima group number when the link is con?gured in ima mode. select the ima group number before enabling the ima mode. when con?guring the link in uni mode after it was in ima mode, do not change the ima group number until the link is reported in uni mode (refer to tx ima mode status register). table 35 - tx link control registers
MT90221 49 address (hex): 0d4- 0d7 direct access 1 register per ima group reset value (hex): 29 bit # type description 7 r/w 0 for stuff indication 1 frame before stuff event. 1 for stuff indication 4 frames before stuff event. 6:3 r/w level over?ow limit. default is 5. 2:0 r/w level under?ow limit. default is 1. table 36 - tx ima control registers address (hex): 0ef direct access reset value (hex): ff bit # type description 7-4 r reserved. read all 1s. 3 r 1 means link 3 is not in ima mode. 2 r 1 means link 2 is not in ima mode. 1 r 1 means link 1 is not in ima mode. 0 r 1 means link 0 is not in ima mode. table 37 - tx ima mode status register
MT90221 50 7.3 tx icp register description tables 38 to 40 describe the tx icp registers. address (hex): 148 direct access controls the transfer of tx icp cells and frame pulse indication reset value (hex): 0f bit # type description 7 r/w when 1 indicates the end of a frame was detected in ima group #3. cleared by writing 0. 6 r/w when 1 indicates the end of a frame was detected in ima group #2. cleared by writing 0. 5 r/w when 1 indicates the end of a frame was detected in ima group #1. cleared by writing 0. 4 r/w when 1 indicates the end of a frame was detected in ima group #0. cleared by writing 0. 3 r/w when 1 indicate that the transfer of the tx icp cell for ima group #3 is complete. write 0 to initiate a transfer. 2 r/w when 1 indicate that the transfer of the tx icp cell for ima group #2 is complete. write 0 to initiate a transfer. 1 r/w when 1 indicate that the transfer of the tx icp cell for ima group #1 is complete. write 0 to initiate a transfer. 0 r/w when 1 indicate that the transfer of the tx icp cell for ima group #0 is complete. write 0 to initiate a transfer. table 38 - tx icp cell handler register address (hex): 149 direct access interrupt enable register for the tx icp handler register reset value (hex): 00 bit # type description 7 r/w write a 1 will enable the generation of an interrupt from the end of a frame detection for ima group 3. a 0 will inhibit the generation of an interrupt. 6 r/w write a 1 will enable the generation of an interrupt from the end of a frame detection for ima group 2. a 0 will inhibit the generation of an interrupt. 5 r/w write a 1 will enable the generation of an interrupt from the end of a frame detection for ima group 1. a 0 will inhibit the generation of an interrupt. 4 r/w write a 1 will enable the generation of an interrupt from the end of a frame detection for ima group 0. a 0 will inhibit the generation of an interrupt. 3 r/w write a 1 will enable the generation of an interrupt when the transfer of the tx icp cell for the ima group 3 is completed. a 0 will inhibit the generation of an interrupt. 2 r/w write a 1 will enable the generation of an interrupt when the transfer of the tx icp cell for the ima group 2 is completed. a 0 will inhibit the generation of an interrupt. 1 r/w write a 1 will enable the generation of an interrupt when the transfer of the tx icp cell for the ima group 1 is completed. a 0 will inhibit the generation of an interrupt. 0 r/w write a 1 will enable the generation of an interrupt when the transfer of the tx icp cell for the ima group 0 is completed. a 0 will inhibit the generation of an interrupt. table 39 - tx icp cell interrupt enable register
MT90221 51 address (hex): 300, 340, 380, 3c0 for ima group 0, 1, 2 and 3 respectively direct access access these locations directly then use transfer command to copy to internal memory reset value (hex): these registers need to be initialized for proper operation cell byte # address offset type description 1-4 00-03 r/w header of icp cell. the values should be set to byte 0: 0x00, byte 1: 0x00, byte 2: 0x00, byte 3: 0x0b. 5 04 r/w hec is always calculated and inserted by the MT90221. 6 05 r/w oam, should be set to 0x01 7 06 r/w cell id, link id. the bit 7 (cell id) is controlled by the MT90221, the link id is provided by the tx link id register. 8 07 r/w ima frame sequence number. inserted by the MT90221. 9 08 r/w icp cell offset. inserted by the MT90221 based on the link offset register info. 10 09 r/w link stuff indication. inserted by the MT90221. 11 0a r/w status & control change indication. inserted by the MT90221. 12 0b r/w ima id 13 0c r/w group status and control 14 0d r/w synchronization information 15 0e r/w tx test control 16 0f r/w tx test pattern 17 10 r/w rx test pattern 18-49 11-30 r/w status and control of links with lid in the range 0-31 50 31 r/w unused 51 32 r/w end-to-end channel 52-53 33-34 r/w crc error control. inserted by the MT90221 table 40 - tx icp cell registers
MT90221 52 7.4 rx registers description tables 41 to 55 describe the receive registers. address (hex): 100 -103 direct access 1 register per link reset value (hex): 0c bit # type description 7 r/w a value of 0 select to count the number of stuff cells received by the physical link. a value of 1 selects to count the total number of cells received by the link. 6 r/w a value of 1 enables the ima mode for this link. a value of 0 enables the uni mode for the link. 5 r/w a value of 1 enables the descrambling of the cell for the link 4 r/w a value of 1 means that the unassigned cells are discarded upon reception. uni mode only. 3 r/w a value of 1 means that the idle cells are discarded upon reception. uni mode only. 2 r/w a value of 1 enables the discard option of the cells with wrong hec. a value of 0 will disables the discard option, all the cells will be written to the receive buffer. 1 r/w a value of 1signi?es that the atm forum polynomial value (coset) is not to be added to the hec before the veri?cation. a value of 0 means that the hec as per i.432 only is calculated and compared (i.e. including the coset). 0 r/w a value of 1 enables the correction of the cells with a wrong hec. a value of 0 disable the correction of the hec. table 41 - rx link control registers address (hex): 109 direct access 1 register for all 4 cell delineation state machines reset value (hex): 67 bit # type description 7:4 r/w delta parameter value for the cell delineation register. the number of consecutive cells with correct hec to leave the presync state to go to the sync state. the default value is 6. 3:0 r/w alpha parameter value for the cell delineation register. the number of consecutive cells with incorrect hec to leave the sync state to go to the hunt state. the default value is 7. table 42 - cell delineation register address (hex): 108 direct access 1 reg. for all 4 cell delineation state machines reset value (hex): 0c bit # type description 7:0 r/w contains the number of consecutive cell periods that the cd circuit will count before the incoming atm cell stream to be considered in lcd state. each count will be done on a cell by cell basis. the value of this register is multiplied by 2 before being loaded in the internal counter. (the internal counter value can be from 0 to 512). note that a value of 0 is not allowed as an lcd condition would be generated. table 43 - loss of cell delineation register
MT90221 53 address (hex): 10a direct access 1 reg. for all 4 ima frame state machines reset value (hex): 91 bit # type description 7:6 r/w alpha parameter value for the ima frame delineation.state machine. the number of consecutive invalid icp cells to leave the ima sync state to go to the ima hunt state.the default value is 2. 5:3 r/w beta parameter value for the cell delineation.state machine. the number of consecutive errored icp cells to leave the ima sync state to go to the ima hunt state. the default value is 2. 2:0 r/w gamma parameter value for the frame delineation state machine. the number of consecutive valid icp cells to leave the ima presync state to go to the ima sync state. the default value is 1. table 44 - ima frame delineation register address (hex): 10c - 10f direct access 1 register per rx ima group reset value (hex): 01 bit # type description 7:0 r/w rx oam label value (de?nes the working rx ima version). table 45 - rx oam label register address (hex): 115 direct access 1 register for the 4 rx links reset value (hex): 00 bit # type description 7-4 r/w reserved. write 0 for normal operation. 3 r/w an oif state was detected on the physical link 3. cleared by writing a 0. 2 r/w an oif state was detected on the physical link 2. cleared by writing a 0. 1 r/w an oif state was detected on the physical link 1. cleared by writing a 0. 0 r/w an oif state was detected on the physical link 0. cleared by writing a 0. table 46 - rx oif status register
MT90221 54 address (hex): 116 direct access 1 register for the 4 rx links reset value (hex): 00 bit # type description 7-4 r/w reserved. write 0 for normal operation. 3 r/w write a 0 to clear the oif counter for physical link 3. 2 r/w write a 0 to clear the oif counter for physical link 2. 1 r/w write a 0 to clear the oif counter for physical link 1. 0 r/w write a 0 to clear the oif counter for physical link 0. table 47 - rx oif counter clear command register address (hex): 117 direct access 1 register to select the link from which to extract the rx icp cells values shown in following registers reset value (hex): 00 bit # type description 7:4 r unused. read all 0s. 3 r reserved. 2:0 r/w selects the rx physical link number to update the values from the rx icp cell. this is used when the rx link is enabled but in uni mode to collect the values received over the icp cells. table 48 - rx load values/link select register address (hex): 118 direct access the value is updated on completion of the write action in the rx load values register reset value (hex): 00 bit # type description 7:0 r this register stores the value of the ima id extracted from the valid rx icp cell received on the link selected in the rx load values/link select register. table 49 - rx link ima id registers
MT90221 55 address (hex): 119 direct access the value is updated on completion of the write action in the rx load values register reset value (hex): 00 bit # type description 7:0 r de?nes the icp cell offset of the link selected in the rx load values/link select register. the signi?cant bits are used depending on the value of m. m=256; bits 7-0 are used, m=128; bits 6-0 are used; m=64; bits 5-0 are used; m=32; bits 4-0 are used. table 50 - rx icp cell offset register address (hex): 11a direct access the value is updated on completion of the write action in the rx load values register reset value (hex): 01 bit # type description 7:0 r this register reports the ima frame sequence number as reported in the last received valid icp cell of the selected link. table 51 - rx link frame sequence number register address (hex): 11b direct access 1the value is updated on completion of the write action in the rx load values register reset value (hex): 00 bit # type description 7:0 r this register reports the scci sequence number as reported in the last received valid icp cell of the link selected in the rx load values/link select register. table 52 - rx link scci sequence number register address (hex): 11c direct access the value is updated on completion of the write action in the rx load values register reset value (hex): 00 bit # type description 7:0 r content of the oif counter for the link selected in the rx load values/link select register. table 53 - rx link oif counter value register
MT90221 56 address (hex): 11d direct access the value is updated on completion of the write action in the rx load values register reset value (hex): 20 bit # type description 7 r lif state of the link selected in the rx load values/link select register. 6 r lcd state of the link selected in the rx load values/link select register. 5 r a value of 1 means that the link selected in the rx load values/link select register is a reference link for his ima group. 4:0 r these bits report the link id number for the link selected in the rx load values/link select register. table 54 - rx link id number register address (hex): 11e direct access the value is updated on completion of the write action in the rx load values register reset value (hex): 00 bit # type description 7:6 r unused. read all 0s. 5:4 r frame length (value of m) of the link selected in the rx load values/link select register. 3:2 r ima frame state: 00: hunt 01: presync 10: sync. 11: stuffed frame event. 1:0 r cell delineation state: 00: hunt 01: presync 10: sync. 11: unused. table 55 - rx state register
MT90221 57 7.5 rx icp cell registers description tables 56 to 59 describe the rx icp registers address (hex): 1c0 direct access access for rx link 3-0 reset value (hex): 00 bit # type description 7:6 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 3. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 5:4 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 2. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 3:2 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 1. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. 1:0 r/w these 2 bits select the type of cells stored in the rx icp cell buffer for physical link 0. 00: valid rx icp cells with changes. 01: all valid rx icp cells. 10: all valid rx cells. 11: no cell written into rx buffer. table 56 - rx icp cell type ram register 1
MT90221 58 address (hex): 1c6 direct access 1 reg. for all 4 rx link fifo reset value (hex): 00 bit # type description 7-4 r/w reserved. write 0 for normal operation. 3 w a value of 1 will increment the position of the read pointer for the physical link 3. a 0 has no effect. 2 w a value of 1 will increment the position of the read pointer for the physical link 2. a 0 has no effect. 1 w a value of 1 will increment the position of the read pointer for the physical link 1. a 0 has no effect. 0 w a value of 1 will increment the position of the read pointer for the physical link 0. a 0 has no effect. table 57 - rx icp cell buffer increment read pointer register address (hex): 1c7 direct access write to bit 2:0 of this register to select the speci?c link rx icp cell fifo. the value is immediately updated for a read reset value (hex): 00 bit # type description 7:6 r unused. read all 0s. 5:4 r level of rx icp cell fifo. 3:2 r fifo write pointer position 1:0 r fifo read pointer position 2:0 w select link number for fifo status. table 58 - rx icp cell level fifo status register address (hex): 1c3 synchronized access set address for an indirect access to write to icp cell ram reset value (hex): 00 bit # type description 7 r/w 0: external sram test mode is disabled, 1: external sram test mode is enabled. 6 r/w reserved, write 0 for normal operation. 5 r/w reserved, write 0 for normal operation. 4 r/w reserved, write 0 for normal operation. 3 r/w reserved, write 0 for normal operation. 2:0 r/w reserved, write 0s for normal operation. table 59 - test mode enable register
MT90221 59 7.6 external sram register description tables 60 to 64 describe the external sram registers. address (hex): 292 direct access de?nes the external sram con?guration reset value (hex): 08 bit # type description 7 r/w write a 1 to reset the receiver. 0 means no action. 6 r/w write a 1 to reset the transmitter. 0 means no action. 5 r/w reserved, write 0 for normal operation. 4:3 r/w write 00 for normal system operation. 2:0 r/w these 3 bits de?ne the size of the external receive memory: 101: 2 banks of 512k x 8 bits 100: 1 bank of 512k x 8 bits 011: 2 banks of 128k x 8 bits 010: 1 bank of 128k x 8 bits 001: 2 banks of 32k x 8 bits 000: 1 bank of 32k x 8 bits table 60 - sram control register address (hex): 283 synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 00 bit # type description 7:0 r/w rx external sram read/write data register. table 61 - rx external sram read/write data address (hex): 291 synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 00 bit # type description 7:0 r/w rx external sram read/write address bit 7:0. table 62 - rx external sram read/write address 0
MT90221 60 address (hex): 290 synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 00 bit # type description 7:0 r/w rx external sram read/write address bit 15:8. table 63 - rx external sram read/write address 1 address (hex): 28f synchronized access set address before the transfer is initiated with the rx external sram control register reset value (hex): 00 bit # type description 7:5 r unused. read all 0s 4 r/w reserved, write 0 for normal operation. 3:0 r/w rx external sram read/write address bit 19:16. table 64 - rx external sram read/write address 2
MT90221 61 7.7 rx delay registers description tables 65 to 74 describe the rx delay registers. address (hex): 280 synchronized access reset value (bin): 1x000000 bit # type description 7 r upon a write to this register, the bit will go to 0 and will return to 1 when the transfer is completed 6 r toggle bit. 5 r/w write 0 to initiate a transfer from the MT90221 registers to the external ram. write 1 to initiate a transfer from the external ram to the MT90221 registers. 4 r/w reserved, write 0 for normal operation. 3 r/w when test mode bit is 1; write 1 to enable the direct addressing mode to the external sram. 2 r/w when test mode bit is 1; write 0 for normal operation.write 1 for disabling all access to the external ram except for the up port (for ram test purposes) 1:0 r/w when bit 1 is 1, there is no access to the external ram (no reset or read or write action to the external ram is done). when bit 1 is 0 and bit 0 is 0, then the external ram is initialized. when bit 1 is 0 and bit 0 is 1, then a read or write access to the external ram is performed, as de?ned by bit 5. table 65 - rx external sram control register address (hex): 281 direct access used to increment or decrement the recombiner delay for an ima group. the value is in the guardband/delta delay register reset value (hex): 00 bit # type description 7 r/w write a 1 to decrement the recombiner delay of ima group #3. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 6 r/w write a 1 to increment the recombiner delay of ima group #3. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 5 r/w write a 1 to decrement the recombiner delay of ima group #2. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 4 r/w write a 1 to increment the recombiner delay of ima group #2. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 3 r/w write a 1 to decrement the recombiner delay of ima group #1. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 2 r/w write a 1 to increment the recombiner delay of ima group #1. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 1 r/w write a 1 to decrement the recombiner delay of ima group #0. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. 0 r/w write a 1 to increment the recombiner delay of ima group #0. the bit will return to 0 when the delay is adjusted. writing a 0 has no effect. table 66 - increment/decrement delay control register
MT90221 62 address (hex): 29d direct access used to initiate an update of the rx delay registers based on the link and delay value to read reset value (hex): 00 bit # type description 7:6 r/w 00: normal delay, 01: read pointer, 10: write pointer. 5 r/w writing a 1 will reset the value of the maximum delay over time register for the selected ima group (see bits 1:0). 4:3 r/w delay register: 11: maximum delay over time 10: current maximum delay for an ima group 01: current minimum delay for an ima group 00: current delay for a link 2 r/w reserved. write 0 for normal operation. 1:0 r/w bits 1:0 are used to specify the physical link or the ima group number. table 67 - rx delay select register address (hex): 284 direct access this register contains the delay value (in number of cells) selected by the rx delay select register. the value always include the current guardband delay reset value (hex): 00 bit # type description 7:6 r/w unused. read all 0s. 5:0 r/w delay value (msb) table 68 - rx delay msb register address (hex): 285 direct access this register contains the delay value (in number of cells) selected by the rx delay select register. the value always include the current guardband delay. reset value (hex): 04 bit # type description 7:0 r/w delay value (lsb). table 69 - rx delay lsb register
MT90221 63 address (hex): 286 direct access this register contains the link number associated with the rx delay value register. reset value (hex): 00 bit # type description 7:2 r/w reserved, write 000100 to these bits for normal operation. 1:0 r/w number of the physical link associated with the value in the rx delay register. this value is not valid when reading the maximum delay over time value is read. table 70 - rx delay link number register address (hex): 288, 28a, 28c, 28e direct access 1 value for each ima group to use for start-up and adding/removing delay (value in number of cells) reset value (hex): 04 bit # type description 7:0 r/w lsb of the guardband/delay value bits 7:0. table 71 - rx guardband/delta delay lsb register address (hex): 287, 289, 28b, 28d direct access 1 value for each ima group to use for start-up and adding/removing delay (value in number of cells) reset value (hex): 00 bit # type description 7:6 r/w unused. read 0 after reset. 5:0 r/w msb of the guardband/delay value bits 13:8. table 72 - rx guardband/delta delay msb register address (hex): 296, 298, 29a, 29c direct access 1 register per ima group (value in number of cells) reset value (hex): 00 bit # type description 7:0 r/w lsb of the maximum operational delay value bits 7:0. table 73 - rx maximum operational delay lsb register address (hex): 295, 297, 299, 29b direct access 1 reg. per ima group (value in number of cells) reset value (hex): 00 bit # type description 7:6 r/w unused. read 0 after reset. 5:0 r/w msb of the maximum operational delay value bits 13:8. table 74 - rx maximum operational delay msb register
MT90221 64 7.8 rx recombiner registers description tables 75 to 79 describe the rx recombiner registers. address (hex): 180 - 183 direct access 1 register per rx link reset value (hex): 00 bit # type description 7:3 r unused. read all 0s. 2 r/w recombiner control: 1 to enable the recombiner and a 0 to disable. this bit works in conjunction with the rx recombiner delay register. 1:0 r/w these 2 bits specify which ima group the link belongs to: 00: ima group #0 01: ima group #1 10: ima group #2 11: ima group #3. table 75 - rx recombiner registers address (hex): 282 direct access 1 register for all links. note: the ?rst link of a group shall not be enabled in delayed recombination mode reset value (hex): 00 bit # type description 7-4 r/w reserved. write 0 for normal operation. 3 r/w a 1 enables the circuitry to wait for the ?rst user cells to be received before adding the link 3 to the recombiner process. a 0 will include the link 3 in the recombiner as soon as it is enabled in the rx recombiner register. 2 r/w a 1 enables the circuitry to wait for the ?rst user cells to be received before adding the link 2 to the recombiner process. a 0 will include the link 2 in the recombiner as soon as it is enabled in the rx recombiner register. 1 r/w a 1 enables the circuitry to wait for the ?rst user cells to be received before adding the link 1 to the recombiner process. a 0 will include the link 1 in the recombiner as soon as it is enabled in the rx recombiner register. 0 r/w a 1 enables the circuitry to wait for the ?rst user cells to be received before adding the link 0 to the recombiner process. a 0 will include the link 0 in the recombiner as soon as it is enabled in the rx recombiner register. table 76 - rx recombiner delay control registers address (hex): 29f direct access reset value (hex): 00 bit # type description 7:4 r/w reserved. 3:0 r/w each bit reports the recombination status for a link. a 1 means that the recombination is enabled. the bit 3 reports for link 3 and so on so forth. do not write to this register. table 77 - enable recombination status
MT90221 65 address (hex): 188 - 18b direct access 1 register per ima group reset value (hex): 00 bit # type description 7 r unused. read 0. 6:4 r reserved. 3 r/w when set to 1, it enables the automatic selection of the reference link for the group. when 0, the link speci?ed in bits 1-0 is used as the reference link. 2 r/w reserved. write 0 for normal operation. 1:0 r/w these 2 bits specify which physical link is to be used as the reference link for the ima group. table 78 - rx reference link control registers address (hex): 18c - 18f direct access 1 register per ima group reset value (hex): 05 bit # type description 7:4 r unused. read all 0s. 3:0 r/w de?nes the integration period for an ima group 1111: reserved. do not use. 1110: 2 21 clock cycles 1101: 2 20 clock cycles 1100: 2 19 clock cycles (preferred value for e1) 1011: 2 18 clock cycles (preferred value for t1 - 24 channels) 1010: 2 17 clock cycles 1001: 2 16 clock cycles (preferred value for t1 - 23 channels) 1000: 2 15 clock cycles 0111: 2 14 clock cycles 0110: 2 13 clock cycles 0101: 2 12 clock cycles 0100: 2 11 clock cycles 0011: 2 10 clock cycles 0010: 2 09 clock cycles 0001: 2 08 clock cycles 0000: 2 07 clock cycles table 79 - rx idcr integration registers
MT90221 66 7.9 tx/rx and pll control registers description tables 80 to 88 describe the tx/rx and pll control registers. address (hex): 080 - 083 direct access 1 reg. per tx link reset value (hex): 00 bit # type description 7:5 r unused. read all 0s. 4 r/w txck and txsync direction: when the bit is 0 (default value) mode 1: txck and txsync are outputs mode 2: txck and txsync are inputs mode 3: txck and txsync are outputs mode 4: txck and txsync are inputs when the bit is 1 mode 5: txck and txsync are inputs mode 6: txck and txsync are outputs mode 7: txck and txsync are inputs mode 8: txck and txsync are outputs 3:0 r/w these 4 bits are used to select the source for the txck for the link: the valid combinations are: 0000: rxck0 0001: rxck1 0010: rxck2 0011: rxck3 1000: refck0 1001: refck1 1010: refck2 1011: refck3 table 80 - tx pcm link control register number 2 address (hex): 088 - 08b direct access 1 reg. per tx link reset value (hex): 00 bit # type description 7 r/w pcm port tri-state control. txclk, txsync and dsto outputs are active when the bit is 1. the outputs of the port is in tri-state if the bit is 0. 6:5 r/w 00: t1, generic mode, 1.544mhz or 2.048 mhz clk, (mode 1 or 5) 01: t1, st-bus mode, 4.096mhz clk, (mode 2 or 6) 10: e1, generic mode, 2.048 mhz clk, (mode 3 or 7) 11: e1, st-bus mode, 4.096mhz clk, (mode 4 or 8) the direction of the txck and txsync signals (i.e.; input or output) is de?ned using the tx pcm link control register #2 bit 4. 4 r/w this bit de?nes the pcm clock rate when one of the 2 t1 generic modes is selected. a 1 signi?es that a 2.048 mhz clock is used and a 0 signi?es that a 1.544 mhz clock is used. this bit is valid only for t1 generic modes (pcm mode 1 or 5). 3 r/w this bit de?nes the position of the pcm channels over the pcm stream. a value of 1 means that the 24 channels are grouped and transmitted in the ?rst 24 channels on the pcm stream. a value of 0 corresponds to using 3 channels every 4 channels. this bit is valid only for t1 type link, in st-bus or generic mode with a txck frequency of 2.048mhz. it is not applicable for t1, generic mode with txck frequency of 1.544mhz. table 81 - tx pcm link control register number 1
MT90221 67 2 r/w t1 signaling channel. a value of 1 disables the use of the channel 24 and reserves it for signaling. a value of 0 enables the use of the 24 channels to carry the cells. valid only for t1 mode. 1 r/w tx clock polarity: rising edge of txck is used to output new data on dsto if bit is 1. falling edge of txck is used to output new data on dsto if bit is 0. valid in generic pcm mode only 0 r/w tx frame pulse polarity. positive if bit is 1, negative if bit is 0. valid in generic pcm mode only. address (hex): 090 - 093 direct access 1 register per rx link reset value (hex): 00 bit # type description 7 r/w pcm input port control. data present at input port is sent to the cell delineation block when the bit is 1. the data at the input port is ignored if the bit is 0. 6 r/w link type: a value of 1 selects the e1 link type and 0 select t1 type. 5 r/w pcm format: a value of 1 selects the st-bus mode and a 0 selects the generic pcm mode. 4 r/w this is the pcm clock rate when the generic mode is selected. a 1 signi?es a 2.048 mhz clock and a 0 signi?es a 1.544 mhz clock. this is valid only for the t1 in generic pcm mode. 3 r/w this bit de?nes the position of the pcm channels over the pcm in stream. a value of 1 means that the 24 channels are grouped and are received in the ?rst 24 channels on the pcm stream. a value of 0 corresponds to 3 channels every 4 channels. valid only for t1 type link, st-bus mode or generic pcm mode with a bit rate of 2.048 mbps. 2 r/w t1 signaling channel. a value of 1 disables the use of the channel 24 and reserves it for signaling. a value of 0 enables the use of the 24 channels to carry the cells. valid only for t1 mode. 1 r/w rx clock polarity: falling edge is used to sample data at dst if bit is 1. rising edge of rxck is used to sample data at dsti if bit is 0. valid in generic pcm mode only 0 r/w rx frame pulse polarity. positive if bit is 1. negative if bit is 0. valid in generic pcm mode only. table 82 - rx pcm link control register address (hex): 088 - 08b direct access 1 reg. per tx link reset value (hex): 00 bit # type description table 81 - tx pcm link control register number 1
MT90221 68 address (hex): 098 direct access reset value (hex): 00 bit # type description 7 r/w writing a 1 forces the deselecting of the selected clock when it failed. 6:5 r/w reserved. set to 0 for normal operation. 4:3 r/w these 2 bits are used to select the source for the signal at pllref1: the valid combinations are: 00: rxck0 01: rxck1 10: rxck2 11: rxck3 2 r/w reserved. write 0 for normal operation. 1:0 r/w these 2 bits are used to select the source for the signal at pllref0: the valid combinations are: 00: rxck0 01: rxck1 10: rxck2 11: rxck3 table 83 - pll reference control register address (hex): 099 direct access reset value (hex): 00 bit # type description 7 r clock running status: cleared by writing to this register, set by the running clock 6 r toggle on every transition of the selected clock 5 r/w reserved.write 0 for normal operation. 4:0 r/w these 5 bits are used to select the clock that is to be veri?ed: the valid combinations are: 00000: refck0 00001: refck1 00010: refck2 00011: refck3 00100: txck0 00101: txck1 00110: txck2 00111: txck3 01100: rxck0 01101: rxck1 01110: rxck2 01111: rxck3 10000: rxck4 10001: rxck5 10010: rxck6 10011: rxck7 table 84 - clock activity register
MT90221 69 address (hex): 09a direct access 1 reg. for all 4 rx links reset value (hex): 00 bit # type description 7:4 r/w reserved. write 0 for normal operation. 3 r/w pcm rx sync signal faulty on link 3. cleared by writing 0. 2 r/w pcm rx sync signal faulty on link 2. cleared by writing 0. 1 r/w pcm rx sync signal faulty on link 1. cleared by writing 0. 0 r/w pcm rx sync signal faulty on link 0. cleared by writing 0. table 85 - rx sync. status register address (hex): 09e direct access 1 reg. for all 4 rx links reset value (hex): 00 bit # type description 7:4 r/w reserved. write 0 for normal operation. 3 r/w pcm tx sync signal faulty on link 3. cleared by writing 0. 2 r/w pcm tx sync signal faulty on link 2. cleared by writing 0. 1 r/w pcm tx sync signal faulty on link 1. cleared by writing 0. 0 r/w pcm tx sync signal faulty on link 0. cleared by writing 0. table 86 - tx sync. status register address (hex): 09c direct access reset value (hex): ff bit # type description 7:4 r reserved. 3 r a 1 signi?es that the tx clock, link 3 is disabled. 2 r a 1 signi?es that the tx clock, link 2 is disabled. 1 r a 1 signi?es that the tx clock, link 1 is disabled. 0 r a 1 signi?es that the tx clock, link 0 is disabled. table 87 - tx clock disabled status address (hex): 09d direct access reset value (hex): 03 bit # type description 7:2 r unused. read 0ss 1 r a 1 signi?es that the pllref1 clock is disabled. 0 r a 1 signi?es that the pllref0 clock is disabled. table 88 - pll ref clock disabled status/device rev
MT90221 70 7.10 counter registers description tables 89 to 93 describe the counter registers address (hex): 214 synchronized access the value in this register is used for internal access to the counter when the transfer command is issued reset value (hex): 00 bit # type description 7:0 r/w a read accesses the msb (byte 3) of the counter selected in the select counter register. a write will hold the value to be written to the selected counter. table 89 - counter byte number 3 register address (hex): 215 synchronized access the value in this register is used for internal access to the counter when the transfer command is issued reset value (hex): 00 bit # type description 7:0 r/w a read accesses the byte #2 of the counter that was selected in the select counter register. a write will hold the value to be written to the selected counter. table 90 - counter byte number 2 register address (hex): 216 synchronized access the value in this register is used for internal access to the counter when the transfer command is issued reset value (hex): 00 bit # type description 7:0 r/w a read accesses the byte #1 (least signi?cant byte) of the counter that was selected in the select counter register. a write will hold the value to be written to the selected counter. table 91 - counter byte number 1 register
MT90221 71 address (hex): 217 synchronized access the value in this register is used for internal access to the counter when the transfer command is issued reset value (hex): 00 bit # type description 7:4 r/w the valid bit combinations are: 1011: utopia input, counter of all cells for link 1010: utopia input, counter of idle cells for link 1001: utopia input, counter of unassigned cells for link 1000: utopia input, counter of cell with hec error, single or multiple bit error 0111: tx link, total number of cells, 0110: tx link, number of idle/filler cells, 0101: tx link, number of stuff cells, 0100: tx link, number of icp cells, 0011: rx link, total number of cells (or stuff cells), 0010: rx link, number of idle/filler cells, 0001: rx link, number of cells with hec errors, 0000: rx link, number of bad icp cells. 3:0 r/w the valid bit combinations are: 1011: ima group 3 when utopia input counter access 1010: ima group 2when utopia input counter access 1001: ima group 1when utopia input counter access 1000: ima group 0when utopia input counter access 0011: link 3 0010: link 2 0001: link 1 0000: link 0 table 92 - select counter register address (hex): 207 synchronized access reset value (bin): 0xx00000 bit # type description 7 r/w write: 0 for normal operation. read: 1 when the transfer is done, 0 when the transfer is pending. 6 r/w reserved, write 0 for normal operation. 5 r/w reserved, write 0 for normal operation. 4 r/w reserved, write 0 for normal operation. 3 r/w value to write to the enable bit. 1 to enable, 0 to mask interrupt. this value is transferred when the bit 1:0 are 10. 2 r/w 0 will enable the transfer from the up to the selected counter. 1 will enable the transfer from the selected counter to the up. 1:0 r/w 00: reserved. do not use. 01: initiate a read or write of the counter value. 10: initiate a read or write of the irq enable counter bit. 11: not used. table 93 - counter transfer command register
MT90221 72 7.11 interrupt registers description tables 94 to 102 describe the interrupt registers. address (hex): 232 direct access reset value (hex): 00 bit # type description 7:4 r reserved. 3:0 r each bit represents a link. a 1 means that the corresponding link has a valid request for interrupt. the level of the irq pin is controlled by the bits in this register and the corresponding bits in the irq master enable register. a write does not have any affect on the bits in this register. the status bit is not latched and changing the mask bit in the irq master register has a direct effect on the level of the irq pin. table 94 - irq master status register address (hex): 218 direct access reset value (hex): 00 bit # type description 7:4 r/w reserved. write 0 for normal operation. 3:0 r/w each bit represents a link. a 1 means that the interrupt form the corresponding link is enabled and that the level of the irq pin is low if the corresponding bit in the irq master register is set. a 0 means that the irq level is not affected by the corresponding bit. table 95 - irq master enable register
MT90221 73 a. bit 7 is present only for link 0. in all other link status registers, this bit is set to 0. b. bit 6 is present only for link 0. in all other link status registers, this bit is set to 0. address (hex): 222 - 225 direct access 1 status register per link reset value (hex): 00 bit # type description 7 a r a 1 in this bit means that at least one of the irq sources from the ima group over?ow status register is requesting service. this bit can be cleared only by service the source of the irq. this bit is valid only for the irq link 0 status register and is reading always a 0 for the irq link 1-3 status registers. 6 b r/w a 1 in this bit means that at least one of the ready bit used to initiate a transfer of a tx icp cell for at least 1 of the ima group is returned to 1 (meaning that the transfer of the tx icp cell is complete) or a frame pulse was detected for an ima group. this bit is cleared by writing a 0 to it. this bit is valid only for the irq link 0 status register and is reading always a 0 for the irq link 1-3 status registers. 5 r/w icp cell with changes received. the link has received an icp cell which contain one or more changes in it. this status bit can be cleared by writing a 0 to it. this bit is set when an icp cell buffer as de?ned in rx icp cell type ram register 1 or 2. 4 r/w iv. the link has received an icp cell which contain a violation as de?ned in table 16 of ima spec. this status bit can be cleared by writing a 0 to it. 3 r/w lods. the link is out of delay synchronization. this status bit can be cleared by writing a 0 to it. 2 r/w lif. loss of ima frame. this status bit can be cleared by writing a 0 to it. 1 r/w lcd loss of cell delineation. this status bit can be cleared by writing a 0 to it. 0 r link counter over?ow interrupt. one or more counters associated with the link over?owed. this status bit can be cleared only by reading or writing to the counter(s) which is (are) the source for the irq. table 96 - irq link status registers address (hex): 219 - 21c direct access 1 enable register per link status reg reset value (hex): 00 bit # type description 7:0 r/w each bit set to 1 will enable the generation of the interrupt when the corresponding bit in the irq link status register is set. table 97 - irq link enable registers address (hex): 235 direct access reset value (hex): xd bit # type description 7:4 r reserved. 3:0 r/w each bit set to 1 represent an over?ow condition from the ima group associated with the bit. there is one bit for each ima group. a bit is set when one or more of the 4 counters or the rx utopia fifo associated with an ima group over?ows. table 98 - irq ima group over?ow status register
MT90221 74 address (hex): 204 direct access reset value (hex): 00 bit # type description 7:4 r unused. should read 0s. 3:0 r/w each bit set to 1 will enable the generation of the interrupt when the corresponding bit in the irq ima group over?ow status register is set. there is one bit for each status bit. table 99 - irq ima group over?ow enable register address (hex): 210 - 213 direct access 1 register per ima group. the rxclk and txclk signals must be active for correct register operation reset value (hex): 00 bit # type description 7:5 r unused. should read 0s. 4 r/w this bit is set when the rx utopia fifo associated with an ima group over?ows. this bit is cleared by writing 0. 3 r/w this bit is set when the counter for all cells associated with an ima group over?ows. (input utopia port). this bit is cleared by writing 0. 2 r/w this bit is set when the counter for idle cells associated with an ima group over?ows. (input utopia port). this bit is cleared by writing 0. 1 r/w this bit is set when the counter for unassigned cells associated with an ima group over?ows. (input utopia port). this bit is cleared by writing 0. 0 r/w this bit is set when the counter for hec errored cells associated with an ima group over?ows. (input utopia port). this bit is cleared by writing 0. table 100 - irq ima over?ow status registers address (hex): 208 - 20b direct access 1 register per link. the rxclk and txclk signals must be active for correct register operation reset value (hex): 00 bit # type description 7:5 r unused. should read 0s. 4 r/w this bit is set when the rx utopia fifo associated with a link in uni mode over?ows. this bit is cleared by writing 0. 3 r/w this bit is set when the utopia input counter for all cells (or all stuff cells event) associated with a link used in uni mode over?ows. this bit is cleared by writing 0. 2 r/w this bit is set when the utopia input counter for idle cells associated with a link used in uni mode over?ows. this bit is cleared by writing 0. 1 r/w this bit is set when the utopia input counter for unassigned cells associated with a link used in uni mode over?ows. this bit is cleared by writing 0. 0 r/w this bit is set when the utopia input counter for hec errored cells associated with a link used in uni mode over?ows. this bit is cleared by writing 0. table 101 - irq utopia uni over?ow status registers
MT90221 75 address (hex): 22a - 22d direct access 1 register per link. the rxclk and txclk signals must be active for correct register operation reset value (hex): 00 bit # type description 7 r/w this bit is set when the tx pcm link counter for all cells associated with a link used in over?ows. 6 r/w this bit is set when the tx pcm link counter for idle or filler cells associated with a link over?ows. 5 r/w this bit is set when the tx pcm link counter for tx stuff cells associated with a link over?ows. 4 r/w this bit is set when the tx pcm link counter for tx icp cells associated with a link over?ows. 3 r/w this bit is set when the rx pcm link counter for all cells (or all stuff cells event) associated with a link over?ows. 2 r/w this bit is set when the rx pcm link counter for idle or filler cells associated with a link over?ows. 1 r/w this bit is set when the rx pcm link counter for hec errored cells associated with a link over?ows. 0 r/w this bit is set when the rx pcm link counter for bad icp cells associated with a link over?ows. table 102 - irq link uni over?ow status registers
MT90221 76 7.12 miscellaneous registers description tables 103 to 105 describe the general status and test register . address (hex): 206 direct access reset value (hex): 10 bit # type description 7:4 r device revision number: reads 0001. 3 r/w set when the utopia output clock is missing or too slow. this latched bit is cleared by writing a 0. 2 r/w set when the utopia input clock is missing or too slow. this latched bit is cleared by writing a 0. 1 r/w over?ow of 1 or more of the tx utopia fifo. 0 r/w set when there is no free cell in tx cell ram. this latched bit is cleared by writing a 0. table 103 - general status register address: 04e direct access reset value (hex): 00 bit # type description 7:0 r/w write 0x60 for normal operation. table 104 - test 1 register address (hex): 0da direct access reset value (hex): 00 bit # type description 7:0 r reserved (different from written values). 7 w write 0 for normal operation. 6 w write 1 for normal operation. 5:4 w write 00 for normal operation 3 w write 1 before adding a link to an existing ima group. write 0 when the link is reported in ima mode. 2 w write 0 for normal operation. 1:0 w write ima group number before adding a link to an ima group. table 105 - test 2 register
m t 9 0 2 2 1 7 7 8 . 0 a p p l i c a t i o n n o t e s i n v e r s e m u l t i p l e x i n g f o r a t m ( i m a ) d i v i d e s a h i g h - b a n d w i d t h s t r e a m o f a t m c e l l s i n a r o u n d - r o b i n f a s h i o n a n d s e n d s t h e m o v e r g r o u p e d t 1 / e 1 l i n e s i n a l o g i c a l c o n n e c t i o n ( o n p u b l i c o r p r i v a t e n e t w o r k s ) a n d r e c o m b i n e s t h e c e l l s t o r e c o v e r t h e o r i g i n a l h i g h - b a n d w i d t h s t r e a m a t t h e r e c e i v i n g e n d . z a r l i n k ' s m t 9 0 2 2 1 i s i d e a l l y s u i t e d t o i m p l e m e n t t h e i m a f u n c t i o n . 8 . 1 c o n n e c t i n g t h e m t 9 0 2 2 1 t o v a r i o u s t 1 / e 1 f r a m e r s m a n y o f f - t h e - s h e l f t 1 / e 1 f r a m e r s r e q u i r e t h e g e n e r a t i o n o f a 1 . 5 4 4 m h z ( t 1 ) o r 2 . 0 4 8 m h z ( e 1 ) t r a n s m i t c l o c k r e f e r e n c e s i g n a l a t a n i n p u t p i n . t h e m t 9 0 4 2 c a n g e n e r a t e b o t h t h e s e c l o c k s a n d t h e s t - b u s b a c k - p l a n e s i g n a l s ( c 4 , f 0 ) . f i g u r e 1 9 p r o v i d e s a n e x a m p l e o f p c m m o d e s 2 a n d 4 i n a n i m a i m p l e m e n t a t i o n u s i n g e x i s t i n g t 1 / e 1 f r a m e r s a n d a c o m m o n 2 m b p s s t - b u s b a c k p l a n e . b u s 4 . 0 9 6 m h z ( c 4 ) c l o c k a n d a f r a m e p u l s e ( f 0 i ) a t t h e t r a n s m i t i n t e r f a c e . a n i n t e r n a l p l l g e n e r a t e s t h e r e q u i r e d 1 . 5 4 4 m h z ( t 1 ) o r 2 . 0 4 8 m h z ( e 1 ) t r a n s m i t c l o c k . f i g u r e 2 0 p r o v i d e s a n e x a m p l e o f p c m m o d e s 2 a n d 4 i n a n i m a i m p l e m e n t a t i o n b a s e d o n t h e z a r l i n k m t 9 0 2 2 1 a n d t h e z a r l i n k m t 9 0 7 4 f r a m e r s . t h i s c o n g u r a t i o n s u p p o r t s c t c m o d e . a l t h o u g h t h e m t 9 0 7 4 u s e t h e s t - b u s f o r m a t b u t i t i s n o t c o n g u r e d a s a c o m m o n b a c k p l a n e . f i g u r e 2 1 e x e m p l i e s p c m m o d e s 2 a n d 4 i n a n i m a i m p l e m e n t a t i o n s u p p o r t i n g t h e a s y n c h r o n o u s l i n k o p e r a t i o n m o d e . e a c h t 1 o r e 1 f r a m e r u s e s i n d e p e n d e n t c l o c k a n d s y n c h r o n i z a t i o n s i g n a l s w h i c h c o r r e s p o n d s t o i t c m o d e . f i g u r e 2 2 e x e m p l i e s p c m m o d e s 1 a n d 3 i n a n i m a i m p l e m e n t a t i o n s u p p o r t i n g t h e a s y n c h r o n o u s l i n k o p e r a t i o n m o d e . e a c h t 1 o r e 1 f r a m e r u s e s i n d e p e n d e n t c l o c k a n d s y n c h r o n i z a t i o n s i g n a l s . n e w g e n e r a t i o n z a r l i n k f r a m e r s o n l y r e q u i r e t h e s t -
m t 9 0 2 2 1 7 8 f i g u r e 1 9 - p c m m o d e 2 a n d 4 : s y n c h r o n o u s s t - b u s m o d e ( u s i n g s t - b u s / 2 . 0 4 8 m b p s b a c k p l a n e c o m p a t i b l e f r a m e r s ) z a r l i n k t 1 / e 1 f r a m e r s m t 9 0 2 2 1 d e v i c e u t o p i a b u s s t - b u s i / f c l o c k s a t m l a y e r b u s t d m b a c k - p l a n e ( s t - b u s ) l e g a c y t r u n k s a t 1 . 5 o r 2 m b p s l e g a c y t r u n k s a t 1 . 5 o r 2 m b p s l e g a c y t r u n k s a t 1 . 5 o r 2 m b p s m t 9 0 4 2 c l o c k r e c o v e r y a n d d e j i t t e r f u n c t i o n s r e c e i v e c l o c k o r 8 k h z r e f e r e n c e s ( 1 . 5 4 4 o r 2 . 0 4 8 m h z ) 8 k h z 4 . 0 9 6 m h z e x i s t i n g d s t o [ 0 : 3 d s t i [ 0 : 3 ] t x c k [ 0 - 3 ] t x s y n c [ 0 - 3 ] r x c k [ 0 - 3 ] r x s y n c [ 0 - 3 ] s t - b u s i / f d a t a d a t a l i n e s s t - b u s i / f d a t a s t - b u s i / f d a t a z a r l i n k t 1 / e 1 f r a m e r s e x i s t i n g z a r l i n k t 1 / e 1 f r a m e r s e x i s t i n g e x t e r n a l s o u r c e d e j i t t e r e d t x c l k t o f r a m e r s ( 1 . 5 4 4 o r 2 . 0 4 8 m h z )
MT90221 79 figure 20 - pcm mode 2 and 4 ctc mode (using mt9074 t1/e1 single chip transceivers) MT90221 device utopia bus dsto c4b f0b dsti rxck[0] dsto[0] dsti[0] txck[0] txsync[0] mt9074/#1 dsto c4b f0b dsti rxck[3] rxsync[3] dsto[3] dsti[3] txck[3] txsync[3] mt9074#n 20 mhz +/-50 ppm level 2 note: the mt9074 #1 is configured in line sync. mode and all other mt9074s are configured in bus master mode. rxsync[0]
m t 9 0 2 2 1 8 0 f i g u r e 2 1 - p c m m o d e 2 a n d 4 : i t c m o d e m t 9 0 2 2 1 d e v i c e u t o p i a b u s d s t o c 4 b f 0 b d s t i r x c k [ 0 ] d s t o [ 0 ] d s t i [ 0 ] t x c k [ 0 ] t x s y n c [ 0 ] m t 9 0 7 4 d s t o c 4 b f 0 b d s t i r x c k [ 3 ] r x s y n c [ 3 ] d s t o [ 3 ] d s t i [ 3 ] t x c k [ 3 ] t x s y n c [ 3 ] m t 9 0 7 4 2 0 m h z + / - 5 0 p p m l e v e l 2 n o t e : a l l m t 9 0 7 4 a r e c o n f i g u r e d i n l i n e s y n c . m o d e r x s y n c [ 0 ] ( u s i n g z a r l i n k m t 9 0 7 4 t 1 / e 1 s i n g l e c h i p t r a n s c e i v e r s )
MT90221 81 figure 22 - pcm mode 1 and 3: generic pcm system interface (for applications with asynchronous lines) t1/e1 framers MT90221 utopia bus atm layer bus legacy trunks at 1.5 or 2 mbps mt9042 transmit clock dejittering function dejittered tx clk legacy trunks at 1.5 or 2 mbps legacy trunks at 1.5 or 2 mbps 1.544 or 2.048 mhz dsto[3] dsti[3] txcki[3] txsynco[3] rxcki[3] rxsynci[3] pcm data (1.544 or 1.544 or 2.048 mhz 1.544 or 2.048 mhz 1.544 or 2.048 mhz dsto[0] dsti[0] txcki[0] txsynco[0] rxcki[0] rxsync[0] 8 khz [t3] 8 khz [t0] 8 khz [r3] 8 khz [r0] pcm data refck0-3 pllref0-1 external source t1/e1 framers t1/e1 framers pcm data 2.048 mhz)
MT90221 82 8.2 optimum usage of 1 bank of memory with a 4 port device due to the addressing mode of the MT90221, only half of the memory locations are utilized when operating in ima mode. this is mainly due to the fact that only links 0 to 3 can be used. with some external circuitry, the addressing can be altered to gain access to the unused half of the memory that would correspond to the links 4 to 7. figure 23 shows how this can be achieved. the cs0 and cs1 signals are merged to generate a unique cs0. the address bit 8 is not modi?ed when bank 0 is accessed and it is inverted when the bank 1 is accessed. the ctrl signal is included to enable or disable the re-mapping circuitry in the case where a layout is including stuf?ng options for an 8 port or a 4 port implementation. if the control feature is not required, the circuitry can be simpli?ed. figure 23 -memory optimization for the MT90221 u5 u6 u9 u10 u1 u2 u3 u4 u8 u7 addro_8 cso_0 ctrl csi_0 csi_1 addri_8 ctrl = 0 -> normal operation ctrl = 1 -> single bank operation note: the two inverters, u9 and u10 here are to make up a small delay to ensure that cso_0 comes after addro_8 when in single bank mode (in this mode, csi_1 is routed to both cso_0 and addro_8)
MT90221 83 9.0 ac/dc characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note: input pins are 5 volt compatible type ? typical ?gures are at 25 c, v dd =3.3v, and for design aid only: not guaranteed and not subject to production testing absolute maximum conditions* parameter symbol min max units 1 supply voltage v dd -0.3 3.9 v 2 voltage at digital inputs v i -1.0 6.5 v 3 current at digital inputs i i -10 10 ma 4 storage temperature t st -40 125 ?c recommended operating conditions - voltages are with respect to ground (vss) unless otherwise stated characteristics sym min typ ? max units test conditions 1 operating temperature t op -40 85 ?c 2 supply voltage v dd 3.0 3.3 3.6 v dc electrical characteristics* - voltages are with respect to ground (vss) unless otherwise stated characteristics sym min typ ? max units test conditions 1 supply current i dd 150 300 ma system clock 25 mhz. pcm clock @ 2.048mhz 2 input high voltage v ih 2.0 5.5 v 3 input low voltage v il -0.5 0.8 v 4 input leakage without pull-up or pull- down i il 110 m av i = 0 to v dd 5 input leakage pins with pull-up i il -35 -115 -214 m a dsti[3:0] refck[3:0] txcki0[3:0] tck txsyncli0[3:0] test1 rxsynci[3:0] tms rxcki[3:0] tdi 6 input leakage pins with pull-down i il 35 115 222 m a test2 7 input pin capacitance c i 10 pf 8 output high voltage v oh 2.4 v 9 output high current i oh -6 ma source v oh =2.4 v, all output and bidirectional pins except external sram and pllref 0 and 1 interface pins. 10 output high current i oh -4 ma source v oh =2.4 v, all external sram and pllref 0 and 1 interface pins 11 output low voltage v ol v ss 0.4 v 12 output low current i ol 6 ma source v ol =0.4 v, all output and bidirectional pins except external sram and pllref 0 and 1 interface pins.
MT90221 84 * dc electrical characteristics are over recommended temperature and supply voltage ? typical ?gures are at 25 c, v dd =3.3v, and for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v, and for design aid only: not guaranteed and not subject to production testing figure 24 - st-bus functional timing diagram 13 output low current i ol 4 ma source v ol =0.4 v, all external sram and pllref 0 and 1 interface pins. 14 output pin capacitance c o 10 pf 15 high impedance leakage i oz -10 1 10 m av o = 0 to v dd ac electrical characteristics ? - pcm port st-bus interface mode - voltages are with respect to ground (vss) unless otherwise stated characteristic sym min typ ? max units test conditions 1 c4i clock width high or low t 4w 110 122 134 ns 2 c4i clock period t 4cyc 244 ns 3 frame pulse setup t fps 30 ns 4 frame pulse hold time t fph 30 ns 5 dsti 0-3 serial input setup t sis 30 ns 6 dsti 0-3 serial input hold t sih 30 ns 7 dsto 0-3 serial output delay t sod 70 ns cl = 150pf 8 dsto 0-3 delay active to high-z t dz 70 ns cl = 150pf 9 dsto 0-3 serial high-z to active t zd 0 10 70 ns cl = 150pf dc electrical characteristics* - voltages are with respect to ground (vss) unless otherwise stated characteristics sym min typ ? max units test conditions st-bus bit cells channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 channel 0 bit 5 at dsti/o 0-3 txsync 0-3/ txck 0-3 rxsync 0-3 rxck 0-3
MT90221 85 figure 25 - st-bus timing diagram t fph t fps txsync 0-3/ rxsync 0-3 t 4w txck 0-3/ rxck 0-3 dsti0-3 t sih t sis dsto0-3 t sod t dz t zd pcm bit stream bit cell bit cell bit cell t 4w t 4cyc
MT90221 86 ? characteristics are over recommended operating conditions unless otherwise stated ? typical ?gures are at 25 c, v dd =3.3v, and for design aid only: not guaranteed and not subject to production testing figure 26 - generic pcm interface timing diagram (frame pulse location) ac electrical characteristics ? - generic pcm interface mode characteristic sym min typ ? max units test conditions 1 txck/rxck clock period for t1, 1.544 mhz mode for e1, 2.048 mhz mode tcyc 648 488 ns duty cycle 40 / 60% 2 txck/rxck clock width high or low for t1, 1.544 mhz mode for e1, 2.048 mhz mode t 4w 260 195 ns 3 frame pulse setup t fps 4ns 4 frame pulse hold t fph 1ns 5 dsti 0-3 serial input setup t sis 3ns 6 dsti 0-3 serial input hold t sih 0ns 7 dsto 0-3 serial output delay t sod 25 ns cl = 150pf 8 txsync/rxsync frame pulse delay after txck/rxck active border t fpd 25 ns cl = 150pf 9 txsync when input (pcm mode 5 & 7) is sampled at the end of the bit period t fpsi 25ns .5 t cyc 10 txsync when input (pcm mode 5 & 7) is sampled at the end of the bit period t fpsh 10ns .5 t cyc txsync0-3/ pcm bit cells channel 24 lsb bit framing bit channel 1 msb bit channel 1 bit 2 rxsync0-3 positive pulse negative pulse bit transmitted at falling edge rising edge bit sampled at txsync0-3/ rxsync0-3 txck0-3/ rxck0-3 txck0-3/ rxck0-3 bit transmitted at rising edge falling edge bit sampled at t1 (1.544 mbps) pcm bit cells channel 31 lsb bit channel 0 msb bit channel 0 bit 2 channel 0 bit 3 e1 (2.048 mbps)
MT90221 87 figure 27 - detailed generic pcm interface timing diagram t1 pcm stream dsti 0-3 channel 24 framing bit channel 1 t sih t fph t fps t sis rxck0-3 rxsync0-3 t 4w t sod bit transmitted with falling edge dsto 0-3 bit sampled with rising edge positive polarity selected t fph t fps rxsync0-3 negative polarity selected rxck0-3 dsti 0-3 t sih t sis t sod bit transmitted with rising edge dsto 0-3 bit sampled with falling edge t cyc t1/e1 pcm stream channel 31 channel 0 channel 0 lsb bit msb bit msb bit bit 2 lsb bit 1.544mhz 2.048mhz txsync0-3 t fpd t 4w positive polarity selected txck0-3 t cyc txck0-3 txsync0-3 negative polarity selected t fpd t fpd t fpd txsync0-3 input t fps i t fpsh txsync0-3 input t fps i t fpsh t fpsh
MT90221 88 note 1 - the rxclk signal needs to be synchronous with the system clock refer to paragraph 5.2. ac electrical characteristics - utopia interface transmit timing signal name dir item description min max txclk a->p txclk frequency (nominal) 0 25 mhz txclk duty cycle 40% 60% txclk peak-to-peak jitter - 5% txclk rise/fall time - 4 ns txdata[7:0], txsoc, txenb*, txaddr[4:0] a->p tt5 input setup to txclk 4 ns - tt6 input hold from txclk 0 ns - txclav[0] a<-p tt7 input setup to txclk 4 ns - tt8 input hold from txclk 0 ns - tt9 signal valid 14 ns - tt10 signal going high impedance 14 ns - tt11 signal going low impedance from txclk 3 ns - tt12 signal going high impedance from txclk 3 ns - ac electrical characteristics - receive timing signal name dir item description min. max. rxclk a->p rxclk frequency (nominal) 0 25 mhz rxclk duty cycle 40% 60% rxclk peak-to-peak jitter - 5% rxclk rise/fall time - 4 ns rxenb*, rxaddr[4:0] a->p tt5 input setup to rxclk 4 ns - tt6 input hold from rxclk 0 ns - rxdata[7:0], rxsoc, rxclav[0] a<-p tt7 input setup to rxclk 4 ns - tt8 input hold from rxclk 0 ns - tt9 1 signal valid 18 ns - tt10 1 signal going high impedance 18 ns - tt11 signal going low impedance from rxclk 3 ns - tt12 signal going high impedance from rxclk 3 ns -
MT90221 89 figure 28 - setup and hold time de?nition figure 29 - tri-state timing clock signal tt5, tt7 tt6, tt8 input setup to clock input hold from clock clock signal valid signal going high impedance t t10 1 signal tt11 signal going low impedance from clock tt12 signal going high impedance from clock t t9 1
MT90221 90 . figure 30 - external memory interface timing - read cycle ac electrical characteristics - external memory interface timing - read access item description min typ max t clk mt90220 system clock period 38 ns 40 ns 46 ns t rc read cycle time 30 ns 1 t clk -10 ns t avrs address setup time 9 ns t avrh address hold time 3 ns t csrs chip select setup time 9 ns t csrh chip select hold time 3 ns t wers write enable* setup time 9 ns t werh write enable* hold time 3 ns t rds data setup time 0 t rdh data hold time 3 t csrs t csrh t avrh t wers t werh t rdh t avrs system clock sr_a[18:0] sr_cs sr_we sr_d[7:0] address valid data valid t rds t rc t clk
MT90221 91 figure 31 - external memory interface timing - write cycle ac electrical characteristics - external memory interface timing - write access item description min typ max t clk system clock period 38 40 ns 46 t wc write cycle time 30 ns 1 t clk -10 ns t avws address setup time 9 ns t avwh address hold time 3 ns t csws chip select setup time 9 ns t cswh chip select hold time 3 ns t wews write enable* setup time 9 ns t wewh write enable* hold time 3 ns t wds data setup time 13 ns t wdh data hold time 3 ns t wews t wewh t wdh system clock sr_a[18:0] sr_cs sr_we sr_d[7:0] note: the sr_we signal stays low until a read cycle is to be performed t clk t avwh t avws address valid t csws t cswh t wc t wds data valid
MT90221 92 9.1 cpu interface timing the cpu interface of the MT90221 supports both the motorola and intel timing modes. no mode select pin is required. with motorola devices, the motorola r/w-signal is connected to the up_r/w* pin and the up_oe* pin is tied to ground. there is no ds signal and the up_cs* signal is taken to be quali?ed with the ds signal. when used with intel devices, the read-signal is connected to the up_oe* pin and the write-signal is connected to the up_r/w* pin. when performing a read operation, data is placed on the bus immediately after up_cs* is low for the motorola timing mode and after the up_cs* and up_ oe*signals are low for intel timing. when performing a write operation in motorola timing mode, the data is clocked into an MT90221 pre-load register on the rising edge of the up_cs* signal. in intel timing mode, the data is clocked into MT90221 pre-load register on the rising edge of the up_r/w* signal. right after that transition, the data is transferred to the MT90221s internal register. writing data into the this register can take up 2 system clock cycles.
MT90221 93 figure 32 - cpu interface timing - read access ac electrical characteristics - cpu interface timing - read cycle characteristics sym min typ max units test conditions 1 r/w set-up time to up_cs* falling edge t ws 1ns 2 data valid after up_ oe*, up_cs* or up_ad t acc 28 ns 3 up_ad or up_r/w* hold time after up_cs rising edge t ah 0ns 4 data hold time after rising edge of up_cs or up_ oe t ch 3ns 5 up_d low impedance after falling edge of up_ oe t oe 2.5 10 ns up_cs address valid t ch up_ad[9:0] up_r/w data valid up_d[7:0] t acc t ch t ws up_ oe t ah t oe
MT90221 94 note 1 - for internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid ac cess. figure 33 - cpu interface motorola timing - write access ac electrical characteristics - cpu interface motorola timing - write cycle characteristics sym min typ max units test conditions 1 up_r/w* set-up time to up_cs* falling edge t ws 1ns 2 address and data set up before rising edge of up_cs* t su 4ns 3 up_ad and data hold time after up_cs rising edge t adh 0ns 4 up_r/w low after rising edge or up_cs t wh 1ns 5 up_cs* high before next up_cs low t csh 2 (see note 1) cycle system clock up_cs address valid up_ad[9:0] up_r/w data valid up_d[7:0] t su t ws up_oe t adh t csh t wh
MT90221 95 note 1 - for internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid ac cess. figure 34 - cpu interface intel timing - write access ac electrical characteristics - cpu interface intel timing - write cycle characteristics sym min typ max units test conditions 1 up_cs* set-up time to up_r/w* falling edge t ws 1ns 2 address and data set up before rising edge of up_r/w t su 4ns 3 up_ad, up_cs and data hold time after up_r/w* rising edge t adh 0ns 4 up_r/w low after rising edge or up_cs t csh 1ns 5 up_cs* high before next up_cs low t wh 2 (see note 1) cycle system clock up_cs address valid up_a[9:0] up_r/w data valid up_d[7:0] t su t ws up_oe t adh t wh (read) (write) t csh
MT90221 96 figure 35 - jtag port timing ac electrical characteristics - jtag port and reset pin timing parameter symbol min typ max units test conditions tck period width t tclk 100 ns bsdl specs 12 mhz tck period width low t tclkl 40 ns tck period width high t tclkh 40 ns tdi setup time to tck rising t disu 2ns tdi hold time after tck rising t dih 33 ns tms setup time to tck rising t mssu 2ns tms hold time after tck rising t msh 5ns tdo delay from tck falling t dod 20 ns c l = 30 pf trst pulse width t trst 15 ns reset pulse width t rst 2 ms 70 mclk cycles t mssu tdi tdo tms tck t disu t msh t dih t dod t tclkh t tclkl t tclk trst t trst
MT90221 97 figure 36 - system clock and reset ac electrical characteristics - system clock and reset parameter symbol min typ max units test conditions clk period width t tclk 38 40 46 ns clk period width low t tclkl 20 ns clk period width high t tdkh 20 ns clk rising t clkr 5ns clk falling t clkf 5ns reset pulse width t rst 10 clk period reset t rst clk t tclkh t tclkl t tclk t clkrl t clklf
MT90221 98 figure 37 - metric quad flat package - 208 pin d d1 e1 e see detail a d1 e1 aa2 pin #1 notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) jedec standard 2.6mm footprint ms-29 5) mqfp-208 package complies to jedec standard ms-29 n q 2 q 3 q 1 q l1 l b1 b c1 c a1
MT90221 99 metric quad flat package dimensions dimensions 208-pin min max a .161 (4.10) a1 0.01 (0.25) a2 .126 (3.20) .142 (3.60) b .007 (0.18) .011 (0.28) b1 .007 (0.18) .009 (0.28) c .003 (0.076) .008 (0.20) c1 .003 (0.076) .006 (0.152) d 1.197 (30.40) 1.212 (30.80) d1 1.098 (27.90) 1.106 (28.10) e .020 bsc (0.5 bsc) e 1.197 (30.40) 1.212 (30.80) e1 1.098 (27.90) 1.106 (28.10) l .018 (0.45) .030 (10.76) l1 .051 ref (1.30 ref) q 07 q 1 0 q 2 516 q 3 516
MT90221 100 list of changes page numbers newer older change text 1 1 replaced: "issue 3" with "issue 4" and "3 april with: 4 december" 2 2 replaced: 00 with: 001 2 2 replaced: 0 with: 1 3 3 changed content 3 3 inserted: overbar above signals 4 4 inserted: overbar to txenb amd rxenb 4 4 deleted: last line in pin 203 description 5 5 inserted: overbar to sr_we, sr_cs_1, 0, up_wr, up_oe, up_rd, up_cs, up_irq 5 5 bolded control signal in pin 198, 199 5 5 changed interface in pin 41 to mode replaced: the last sentence in pin 41 to read, "de-asserting this signal to high will... 5 5 replaced: the last two sentences in pin 39 to read, "de-asserting this signal to high will.... 6 6 replaced: "2.048 mbit/s" with "1.544 mbps" and "1.533 mbps" with "2.048 mbits" in pin 81, 88, 90, 97... 6 6 replaced: "2.048 mbit/s" with "1.544 mbps" and "1.533 mbps" with "2.048 mbits" in pin 118, 124, 127... 6 6 replaced: "rxck" with "txck" 6 6 inserted : "pcm in front of section 4.2...in pin 80, 87, 89.... 6 6 replaced: "rxck0" with "rxcki" and replaced "c4" with "4.096 mhz" in pin 120, 122, 129... 7 7 replaced: tristate with: tms 14 13 replaced: the scci ?eld is incremented with: the scci ?eld is incremented 14 14 replaced: ima group with: ima 14 14 inserted: (note: the startup procedure 14 14 replaced: sent. with: sent. note that the test 14 14 replaced: disabling with: ?rst disabling the source 16 16 inserted: a value of 360 in 16 16 inserted: the lcd status bit is 16 16 deleted: a value of 360 in 18 17 replaced: s/w with: software 18 18 inserted: the lif status bit is 18 18 replaced: 7) with: 7, o-19 optional requirements) 18 18 inserted: "vaid icp cell..." 19 19 inserted: mode 19 19 replaced: register and with: register, 19 19 inserted: to 1 and the bit 19 19 inserted: "when this option... to the last paragraph of 3.3.7 20 20 replaced: enable with: enabled 20 20 replaced: disruptions. with: disruptions and the smallest allowed 20 20 replaced: the programmed with: the programmed 20 20 inserted: "a delay is negative... after the ?rst sentence in 3.3.10.3 21 20 replaced: will go below the guardband with: result in a negative delay 21 20 inserted: current 21 20 replaced: delay with: delay 21 21 replaced: registers): with: registers). 21 21 inserted: (note: the startup procedure 22 21 replaced: decreases with: decreases or
MT90221 101 22 22 replaced: 5 with: 6 30 29 replaced: used. with: used for any mt90220 port. 30 30 inserted: the cell available satus line ( 30 30 replaced: port. with: port in mphy mode. 31 31 inserted: in this mode, the bit 33 32 replaced: information: with: information and are active as 33 32 replaced: link with: link, , with good or bad 38 37 replaced: 0eb with: 0ef 42 41 replaced: ho with: no 45 44 replaced: hex): with: bin): 47 46 replaced: mode with: mode (adaptive) algorithm 47 46 replaced: mode with: mode (?xed) algorithm 51 51 inserted: "by the mt90220... in cell byte #14 60 59 replaced: write 01 with: write 00 62 61 replaced: hex): with: bin): 75 73 inserted: "this bit is set... to bit #5 79 77 replaced: "general status register" with "general status and test register 90 90 updated: figure 27 93 91 replaced: 2 with: 1 93 91 removed: 2nd line of table 93 91 figure updated for 2 clock cycles access time 94 92 replaced: 2 with: 1 94 92 removed: 2nd line of table 94 92 figure updated for 2 clock cycles access time 99 97 replaced: 10 with: 5 99 97 replaced: 10 with: 5 99 97 replaced: 10 clk period with: 10 99 97 replaced: ns with: clk period
MT90221 102 list of abbreviations and acronyms aal atm adaptation layer atm asynchronous transfer mode cbr constant bit rate cdv cell delay variation cpe customer premises equipment crc cyclic redundancy check ctc common transmit clock dsu data service unit fe far end gsm group state machine gtsm group transmit state machine hec header error control idcr ima data cell rate i/f interface ifsm ima frame state machine ima inverse multiplexing for atm isdn integrated services digital network itc independent transmit clock lcd loss of cell delineation lid link identi?cation lif loss of ima frame lods link out of delay synchronization lof loss of frame los loss of signal lsm link state machines m ima frame size mib management information base mvip multi-vendor integration protocol ne near end oam operations, administration and maintenance ocd out of cell delineation (anomaly) oif out of ima frame (anomaly) pdh plesiochronous digital hierarchy phy physical layer pmd physical medium dependent qos quality of service rai remote alarm indication rdi remote defect indication rfi remote failure indication sar segmentation and reassembly scci status and control change indication soc start of cell tc transmission convergence trl timing reference link trlcr timing reference link cell rate utopia universal test and operations physical interface for atm uni user network interface atm glossary asynchronous transfer mode adaptation layer (aal) - standardized protocols used to translate higher layer services from multiple applications into the size and format of an atm cell. individual protocols are indexed as per the examples below: aal0 - native atm cell transmission propri- etary protocol featuring 5-byte header and 48- byte user payload. aal1 - used for the transport of constant bit rate, time-dependent traf?c (e.g. voice, video); requires transfer of timing information between source and destination; maximum of 47-bytes of user data permitted in payload as an addi- tional header byte is required to provide sequencing information. aal5 - usually used for the transport of vari- able bit rate, delay-tolerant data traf?c and sig- nalling which requires little sequencing or error-detection support. active - this is a link state indicating the link is capable of passing atm layer cells in the speci?ed direction. aligned - ima frames are said to be aligned if they are transmitted simultaneously. asynchronous 1. not synchronous; not periodic. 2. the temporal property of being sourced from independent timing references, having different frequencies and no ?xed phase relationship 3. in telecommunications, data which is not synchronized to the public network clock. 4. the condition or state of being unable to determine exactly when an event will transpire prior to its occurrence. asynchronous transfer mode (atm ) - a method of organizing information to be transferred into ?xed-
MT90221 103 length cells; asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. note: although atm cells are transmitted synchronously to main- tain the clock between sender and receiver, the sender transmits data cells on an as available basis and transmits empty cells when idle. the sender is not limited to transmitting data every nth cell. blocked - the blocked state is a group state indicating that the group has been inhibited. blocking - blocking is a transitional state that allows graceful transition into the unusable state without loss of atm layer cells. cell - fixed-size information package consisting of 53 bytes (octets) of data; of these, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead. cell delay variation (cdv ) - a qos parameter that measures the peak-to-peak cell delay through the network; results from buffering and cell scheduling. common transmit clock (ctc) con?guration - this is a con?guration where the transmit clocks of all links within the ima group are derived from the same clock source. constant bit rate - an atm service category supporting a constant or guaranteed rate, with timing control and strict performance parameters. used for services such as voice, video, or circuit emulation. filler cell - a filler cell is used to ?ll in the ima frame when no cells are available at the atm layer. it is used for performing cell rate decoupling at the ima sublayer (e.g., similar to the idle cell used in single link interfaces). header error control (hec) - atm equipment (usually the phy) uses the ?fth octet in the atm cell header to check for an error and correct the contents of the header; crc algorithm allows for single-error correction and multiple-error detection. i.363 - itu-t recommendation specifying the aals for b-isdn. ima frame - the ima frame is used as the unit of control in the ima protocol. it is de?ned as m consecutive cells, on each of n links, where 1 n 32 (determined by the um and ima link start-up procedure), in an ima group. one of the m cells on each of the n links is an icp cell that occurs within the frame at the icp cell offset position. this offset position may be different between links. the ima frame is aligned on all links. differential link delay can cause the reception to be mis-aligned in time. alignment can be recovered using a link delay synchronization mechanism. the icp stuff mechanism is a controlled violation of the ima consecutive frame de?nition. ima group - the ima group is a group of links at one end of a circuit that establish an ima virtual link to another end. ima sublayer - the ima sublayer is part of the physical layer that is located between the interface speci?c transmission convergence sublayer and the atm layer. ima virtual link - the ima virtual link is a virtual circuit established between two ima ends over a number of physical links (i.e., ima group). inhibiting - inhibiting is a voluntary action that disables the capacity of a group or link to carry atm layer cells for reasons other than reported problems. insuf?cient links - this is a group state indicating that the group does not have suf?cient links to be in the operational state. independent transmit clock (itc) con?guration - this is a con?guration where the transmit clock of at least one link within the ima group is not derived from a common clock source. isochronous - the temporal property of an event or signal recurring at known periodic time intervals (e.g. 125 m s). isochronous signals are dependent on some uniform timing, or carry their own timing information embedded as part of the signal. examples are ds-1/t1 and e1. from the root words, iso meaning equal, and chronous meaning time. itu-t - international telecommunications union telecommunications standards sector. layer management functions - the layer management functions relate to processing of actions such as con?guration, fault monitoring and performance monitoring within the group. loss of cell delineation (lcd) - the lcd defect is reported when the ocd anomaly persists for the period of time speci?ed in itu-t recommendation i.432(30)?. the lcd defect is cleared when the ocd anomaly has not been detected for the period of time speci?ed in itu-t recommendation i.432.
m t 9 0 2 2 1 1 0 4 l c d r e m o t e f a i l u r e i n d i c a t i o n ( l c d - r f i ) - t h e l c d - r f i i s r e p o r t e d t o t h e f e w h e n a l i n k d e f e c t i s l o c a l l y d e t e c t e d . t h e l c d - r f i d e f e c t i s n o t a l w a y s r e q u i r e d o n t h e l i n k i n t e r f a c e . l i n k d e l a y s y n c h r o n i z a t i o n ( l d s ) - t h e l d s i s a n e v e n t i n d i c a t i n g t h a t t h e l i n k i s s y n c h r o n i z e d w i t h t h e o t h e r l i n k s w i t h i n t h e i m a g r o u p w i t h r e s p e c t t o d i f f e r e n t i a l d e l a y . l o s s o f i m a f r a m e ( l i f ) d e f e c t - t h e l i f d e f e c t i s t h e o c c u r r e n c e o f p e r s i s t e n t o i f a n o m a l i e s f o r a t l e a s t g a m m a + 2 i m a f r a m e s . l i n k o u t o f d e l a y ( l o d s ) s y n c h r o n i z a t i o n d e f e c t - t h e l o d s i s a l i n k e v e n t i n d i c a t i n g t h a t t h e l i n k i s n o t s y n c h r o n i z e d w i t h t h e o t h e r l i n k s w i t h i n t h e i m a g r o u p . m u l t i - v e n d o r i n t e g r a t i o n p r o t o c o l ( m v i p ) - m v i p s t a n d a r d s a r e d e s i g n e d t o s u p p o r t t h e i n t e r - o p e r a b i l i t y o f p r o d u c t s f r o m d i f f e r e n t m a n u f a c t u r e r s a n d t h e p o r t a - b i l i t y o f c o m p u t e r s o f t w a r e b e t w e e n p r o d u c t s f r o m d i f - f e r e n t m a n u f a c t u r e r s w i t h t h e g o a l o f f a c i l i t a t i n g n e w a n d i m p r o v e d a p p l i c a t i o n s o f c o m p u t e r a n d c o m m u n i - c a t i o n s e q u i p m e n t . o u t o f c e l l d e l i n e a t i o n ( o c d ) a n o m a l y - a s s p e c i - e d i n i t u - t r e c o m m e n d a t i o n i . 4 3 2 ( 3 0 ) , a n o c d a n o m a l y i s r e p o r t e d w h e n a l p h a c o n s e c u t i v e c e l l s w i t h i n c o r r e c t h e c a r e r e c e i v e d . i t c e a s e s t o b e r e p o r t e d w h e n d e l t a c o n s e c u t i v e c e l l s w i t h c o r r e c t h e c a r e r e c e i v e d . o u t o f i m a f r a m e ( o i f ) a n o m a l y - t h e o i f i s t h e o c c u r r e n c e o f a n i m a a n o m a l y a s d e n e d i n t h e i n v e r s e m u l t i p l e x i n g f o r a t m s p e c i c a t i o n . o p e r a t i o n a l - t h e o p e r a t i o n a l s t a t e i s a g r o u p s t a t e t h a t h a s s u f c i e n t l i n k s i n b o t h t h e t r a n s m i t a n d r e c e i v e d i r e c t i o n s t o c a r r y a t m l a y e r c e l l s . p l e s i o c h r o n o u s - t h e t e m p o r a l p r o p e r t y o f b e i n g a r b i t r a r i l y c l o s e i n f r e q u e n c y t o s o m e d e n e d p r e c i - s i o n . p l e s i o c h r o n o u s s i g n a l s o c c u r a t n o m i n a l l y t h e s a m e r a t e , a n y v a r i a t i o n i n r a t e b e i n g c o n s t r a i n e d w i t h i n s p e c i c l i m i t s . s i n c e t h e y a r e n o t i d e n t i c a l , o v e r t h e l o n g t e r m t h e y w i l l b e s k e w e d f r o m e a c h o t h e r . t h i s w i l l f o r c e a s w i t c h t o o c c a s i o n a l l y r e p e a t o r d e l e t e d a t a i n o r d e r t o h a n d l e b u f f e r u n d e r - o w o r o v e r o w . ( i n t e l e c o m m u n i c a t i o n s , t h i s i s k n o w n a s a f r a m e s l i p ) . p h y s i c a l l a y e r ( p h y ) - b o t t o m l a y e r o f t h e a t m r e f - e r e n c e m o d e l ; p r o v i d e s a t m c e l l t r a n s m i s s i o n o v e r t h e p h y s i c a l i n t e r f a c e s t h a t i n t e r c o n n e c t t h e v a r i o u s a t m d e v i c e s . q u a l i t y o f s e r v i c e ( q o s ) - a t m p e r f o r m a n c e p a r a m e - t e r s t h a t c h a r a c t e r i z e t h e t r a n s m i s s i o n q u a l i t y o v e r a g i v e n v c ( e . g c e l l d e l a y v a r i a t i o n ; c e l l t r a n s f e r d e l a y , c e l l l o s s r a t i o ) . s t u f f e v e n t - t h e s t u f f e v e n t i s t h e r e p e t i t i o n o f a n i c p c e l l o v e r o n e i m a l i n k t o c o m p e n s a t e f o r a t i m i n g d i f f e r e n c e w i t h o t h e r l i n k s w i t h i n t h e i m a g r o u p . s y n c h r o n o u s 1 . t h e t e m p o r a l p r o p e r t y o f b e i n g s o u r c e d f r o m t h e s a m e t i m i n g r e f e r e n c e . s y n c h r o n o u s s i g n a l s h a v e t h e s a m e f r e - q u e n c y , a n d a x e d ( o f t e n i m p l i e d t o b e z e r o ) p h a s e o f f s e t . 2 . a m o d e o f t r a n s m i s s i o n i n w h i c h t h e s e n d i n g a n d r e c e i v i n g t e r m i n a l e q u i p - m e n t a r e o p e r a t i n g c o n t i n u a l l y a t t h e s a m e r a t e a n d a r e m a i n t a i n e d i n a d e s i r e d p h a s e r e l a t i o n s h i p b y a n a p p r o - p r i a t e m e a n s . u n i v e r s a l t e s t a n d o p e r a t i o n s p h y s i c a l i n t e r f a c e f o r a t m ( u t o p i a ) - a p h y - l e v e l i n t e r f a c e t o p r o v i d e c o n n e c t i v i t y b e t w e e n a t m c o m p o n e n t s . u n u s a b l e - t h e u n u s a b l e s t a t e i s a l i n k s t a t e i n d i c a t - i n g t h a t a l i n k i s n o t i n u s e d u e t o a f a u l t , i n h i b i t i o n , e t c . u s a b l e - t h e u s a b l e s t a t e i s a l i n k s t a t e i n d i c a t i n g t h e l i n k i s r e a d y t o o p e r a t e i n t h e s p e c i e d d i r e c t i o n , b u t i s w a i t i n g t o m o v e t o t h e a c t i o n s t a t e . v i r t u a l c h a n n e l ( v c ) - o n e o f s e v e r a l l o g i c a l c o n n e c - t i o n s d e n e d w i t h i n a v i r t u a l p a t h ( v p ) b e t w e e n t w o a t m d e v i c e s ; p r o v i d e s s e q u e n t i a l , u n i d i r e c t i o n a l t r a n s - p o r t o f a t m c e l l s . a l s o v i r t u a l c i r c u i t . g l o s s a r y r e f e r e n c e s : t h e a t m g l o s s a r y - a t m y e a r 9 7 - v e r s i o n 2 . 1 , m a r c h 1 9 9 7 t h e a t m f o r u m g l o s s a r y - m a y 1 9 9 7 a t m a n d n e t w o r k i n g g l o s s a r y ( h t t p : / / w w w . t e c h g u i d e . c o m / c o m m / i n d e x . h t m l ) t e r m s - m a y 1 9 9 5 . z a r l i n k s e m i c o n d u c t o r g l o s s a r y o f t e l e c o m m u n i c a t i o n s
MT90221 105 notes:
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